ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers

ReVEAL: GNN-Guided Reverse Engineering for Formal Verification of Optimized Multipliers Chen Chen1, Daniela Kaufmann2, Chenhui Deng3, Zhan Song1, Hongce Zhang4, and Cunxi Yu1 1 University of Maryland, College Park, USA {cchen099, zhansong, cunxiyu}@umd.edu 2 TU Wien, Austria daniela.kaufmann@tuwien.ac.at 3 NVIDIA cdeng@nvidia.com 4 Hong Kong University of Science and Technology (Guangzhou) hongcezh@hkust-gz.edu.cn Abstract. We present ReVEAL, a graph-learning-based method for reverse engineering of multiplier architectures to improve algebraic cir- cuit verification techniques. Our framework leverages structural graph features and learning-driven inference to identify architecture patterns at scale, enabling robust handling of large optimized multipliers. We demonstrate applicability across diverse multiplier benchmarks and show improvements in scalability and accuracy compared to traditional rule- based approaches. The method integrates smoothly with existing verifi- cation flows and supports downstream algebraic proof strategies. Keywords: Reverse engineering · Multiplier · Graph learning · Formal verification · Computer algebra 1 Introduction Gate-level arithmetic circuits, in particular integer multipliers that have been optimized via logic synthesis, continue to pose significant challenges for cur- rent formal verification techniques. Despite notable advancements in computer algebra-based (CA) techniques [8,14,17,21], these methods often rely on syntac- tic heuristics and hence struggle with synthesized circuits due to optimizations that obscure their original word-level structure [7,17,21,32,33]. Our goal is to verify such optimized circuits by reverse-mapping them back to their original non-optimized word-level representations that can be efficiently verified using algebraic reasoning. We ensure the correctness of this mapping through Boolean satisfiability (SAT)-based equivalence checking. Traditional computer algebra techniques reduce the task of circuit verifica- tion to an ideal membership test for the specification polynomial, typically uti- lizing Gröbner bases [5] to simplify the polynomials through backward rewriting. In [13,14], an incremental column-wise verification approach together with adder arXiv:2512.22260v1 [cs.LO] 24 Dec 2025 2 Authors Suppressed Due to Excessive Length

AIG/BLIF Low Scalability High Memory Usage High Runtime High Scalability LOW Memory Usage Efficient Runtime

SAT+CA Atomic Blocks Reconstruction Abstraction-level Multiplier Architecture Inference CA GNN+SAT+CA ReVEAL Conventional Tools Fig. 1: Overview of ReVEAL versus Conventional Tools substitution is used in the tool AMulet2 to handle unoptimized multipliers. However, the verification of optimized multipliers still presents significant chal- lenges due to blow-ups in the intermediate rewriting steps. In RevSCA2 [21] this is addressed by algebraic reverse engineering to recover word-level components such as full adders and half adders. Most recently, DynPhaseOrderOpt [17] optimizes the encoding of the phases of occurring signals to enhance backward rewriting and keep the sizes of intermediate polynomials small. However, de- spite these advances, logic synthesis often applies aggressive optimizations that obscure the original circuit structure. As a result, many original atomic blocks cannot be restored through cut enumeration, which limits the effect of the afore- mentioned rewriting methods. Moreover, the inevitable occurrence of numerous OR chains and XOR gates in multiplier circuits further complicates polynomial rewriting, resulting in ongoing issues with monomial blow-ups. Recent work by Li et al. [19] reconstructs an adder tree from optimized mul- tipliers to build a structurally similar reference design, and then verifies it via CA and SAT-based equivalence checking. However, such reconstruction-based reverse engineering fundamentally depends on explicit structural pattern match- ing, which is fragile under aggressive synthesis and technology mapping. As a result, boundary recovery can become expensive or fail entirely, and the approach is often architecture-specific (e.g., tailored to adder trees), making it difficult to handle diverse designs such as 4-2/compressor and counter-based Wallace trees, XOR-heavy addition structures, or Booth-encoded multipliers where PPG/PPA boundaries are blurred. Due to the above limitations of reconstruction-based methods [19], ReVEAL instead formulates the task as a learning-based inference problem. Traditional re- verse engineering largely depends on recovering explicit boundaries and subgraph patterns, which can be broken or smeared by aggressive synthesis. In contrast, GNNs can aggregate information over neighborhoods via message passing and encode both local motifs and broader connectivity trends, allowing ReVEAL to capture more optimization-invariant cues from the netlist graph and thus remain effective even when canonical structures are not directly re

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