The conventional two transistor astable multivibrator has been modified to produce better waveform which are more steeply rising and falling than those from the conventional astable. The improvement in the waveform is achieved by using a diode pair in each collector branch of the transistors. This restricts the direction of current flow for the charging and discharging of the timing capacitors. This article also derives the time period of oscillations for the modified circuit and discusses the limits on source and sink currents at the transistor collectors.
The conventional two transistor astable (Giacoletto 1977;Kasatkin & Nemtsov 1986) as shown in Figure 1 finite time required by the capacitor to charge to the full voltage allowed by the branch the voltage at the collector does not increase sharply and exhibits a slow rise in the output waveform(Figure 1 right) depending on the R C C time constant. Even though reducing the value of R C seems to be a possible solution is not always acceptable. As this would drain more power in the circuit. Here an alternate solution is proposed which improves the wave form without having to reduce the value of R C . This circuit is as shown in Figure 2. This article is divided into three sections the first gives introduction to the problem, section II describes the modified circuit along with the important results of analysis of the circuit and the III rd section presents test results. Appendix at the end of the article documents the analysis through which results in section II were reached.
The waveforms obtained from an ordinary transistorized astable have been improved by giving a different path for the charging of the timing capacitors. While the capacitors are discharged by the collectors through D1 and D2 respectively they will be charged through the diodes D1’ and D2’ respectively, avoiding the paths involving the collectors. The improved astable works exactly 2
where n is the number of diodes in the R c branch, here only one (D1’ and D2’, D1 and D2 are for the waveform improvement alone and do not count in n).
However in the asymmetric case, due to incomplete charging of the larger time constant capacitor the above formula does not hold good due to failure of the assumption that the larger time constant capacitor was fully charged during the previous phase to the allowed value in the branch.
So in the asymmetric case, t on S ≈ 0. 62R b S C S , for V=5 .5 and n=1
where the superscripts/subscripts L and S represent the side with large and small value of time constant , R b C , respectively. These formulae have been tested both by simulation and by building the circuit. They are in very good agreement with experimental values.
We first try to understand the operation of the circuit qualitatively. One can note that the capacitors charge through R C while discharge through R b . Hence the capacitor is considered to be always fully charged to the allowed value in the branch due to the low value of R C compared to R b . In the schematic above the charge(blue) and discharge(red) paths have been shown. However in the case where there is an asymmetry in the values of C S and C L the charging of C L can be incomplete due to its larger value. So it follows that in the symmetric case when C S =C L =C and R b S =R b L =R b the time period of transistors on either side can simply be taken to be the discharge time of the respective capacitors untill a swap in the on state of the transistors occurs. As we know to turn on a transistor we need a voltage of ~0.6V across the BE junction. From the schematic it can be seen that this voltage is provided by D1 or D2 for the Q2 and Q1 respectively. For argument sake if we consider Q2 to be off and Q1 to be in the on state. Then we have a situation where a reverse charge on C S exists due to a previous state which is now decaying through the path shown in the figure. The transistor Q2 remains off untill the sum of voltages on C S and D1 are less than 0.6V. This means the capacitor C S has to fully discharge i.e V C S = 0 for Q2 to just turn on. This further simplifies the problem since we now know both the initial charge on the capacitor and the decay path for C S and like wise for C L in the symmetric case. The peak reverse charge on C S can be obtained by observing the schematic. Since R C is small we assume that the capacitor is fully charged in a short time to the residual voltage after accounting for the voltage drops across n S diodes and the BE junction of Q2.
i.e
V C S = V -n S 10.7
(1)
Here the voltage drop across the diodes and BE junction of transistor Q2 has been chosen to be 0.7V however at lower supply voltages(< 3.0V) 0.6V may be a better choice. With this reverse charge on the capacitor C S , t on (2)
which is rearranged to obtain t on S as ,
In the all symmetric case t on 5) equation ( 5) gives the peak reverse voltage on C L put on it during t on S . We can now obtain the time period t on L by the requirement that C L discharges fully through a decay loop similar to C S . We write by observing the schematic a similar equation like (2) for the discharge of C L as ,
we rearrange (6) to obtain t on L as ,
where V C L can be obtained from (5). We see from ( 4) & ( 7) that in the symmetric case t on L = t on S .
Note : Recommended operation n S =n L .
Next the current sink and source capabilities are discussed. When the transistor from which the signal is tapped is on the current sinks into the collector. This current should be such that the collector can sti
This content is AI-processed based on open access ArXiv data.