Complexity of basic boolean operators for digital circuit design

This article provides a survey of circuit complexity bounds for basic boolean transforms exploited in digital circuit design and efficient methods for synthesizing such circuits. The exposition covers structurally simple functions and operators, such as counters, adders, encoders, and multiplexors, and excludes more complex algebraic operations with numbers, polynomials, and matrices. Several applications to implementing more specific operations are also discussed.

💡 Research Summary

The paper presents a comprehensive survey of circuit‑complexity results for a set of elementary Boolean operators that are ubiquitous in digital hardware design, such as counters, adders, encoders, multiplexers, comparators, and related transforms. The author adopts the standard model of Boolean circuits built from a basis of all binary Boolean functions, defines the size of a circuit C(Φ) as the number of non‑input gates, and the depth D(Φ) as the length of the longest input‑to‑output path. A parallel‑complexity measure C_log(F) is introduced to capture the cost of implementing an operator F with depth O(log n), where n is the number of input variables.

The survey proceeds operator by operator, providing both upper and lower bounds for the minimal size and for the parallel size. For prefix sums (PREF) and suffix sums (PS) over a binary associative operation (∧, ∨, ⊕), the classic Brent‑Kung (Ofman) construction yields C = n − 1 and C_log = 2n − Θ(log n); the lower bound C + D ≥ 2n − 2 shows this is essentially optimal. Increment (INC) and decrement (DEC) circuits are built by expressing each output bit as a XOR of the input bit and the conjunction of all lower‑order bits; using a prefix‑AND circuit gives C ≤ 2n − 2 and a parallel implementation with C_log ≤ 3n − Θ(log n). An up‑down counter (UDC) combines the two, achieving C ≤ 3n − 3 and C_log ≤ 4n − Θ(log n).

The Gray‑code counter (GRC) is realized by converting a binary index to Gray code (via prefix‑XOR), incrementing in binary, then converting back. This yields C ≤ 4n − 7 and C_log ≤ 6n − Θ(log n). Carry generation (CAR) is reduced to a prefix computation over a custom associative operator ⋆ on 2‑bit vectors; since ⋆ can be implemented with three basic gates, the parallel carry circuit satisfies C = 2n − 2 and C_log ≤ 5n − Θ(log n). Adding two n‑bit numbers (ADD) simply attaches an XOR layer to the carry circuit, giving the tight bound C = 5n − 3 (proved by Red’kin) and C_log ≤ 8n − Θ(log n). Subtraction is handled implicitly via two’s complement.

Comparator (CMP) reuses the carry structure: the most significant carry bit equals the result of A > B, leading to C ≤ 4n − 3 and C_log ≤ 5n − Θ(log n). An extended comparator (CMP*) that also outputs equality adds only a linear number of extra gates, keeping C_log ≤ 5n − 3. Maximum (MAX) and minimum (MIN) are obtained by feeding the comparator’s decision bit into a bitwise selector; this adds a layer of 2n gates, giving C ≤ 6n − 3 and C_log ≤ 7n ‑ Θ(log n).

The decoder (DEC) that produces a one‑hot vector from a binary address is implemented by recursively splitting the address bits and AND‑ing the corresponding halves, which leads to a parallel depth of C_log ≤ n + Θ(√n) and a matching lower bound. The demultiplexer (DEC*) and multiplexer (MUX) differ only by a few extra control‑gate connections, so their complexities differ by at most a constant factor.

Table 1 in the paper summarizes all these bounds. The author also illustrates how these primitives can be combined to build more sophisticated structures such as a two‑selector, a weight‑preserving counter, multiple selection networks, and a bit‑pair permutation circuit. Throughout the survey, the author emphasizes that while asymptotic results give a clear picture for large n, the simple constructions described often perform very well even for modest input sizes, making them highly relevant for practical digital design. The overall conclusion is that most basic Boolean operators can be efficiently realized using prefix‑sum techniques and associative‑operator reductions, providing both near‑optimal size and logarithmic depth in a uniform synthesis framework.