Measurement-Free Ancilla Recycling via Blind Reset: A Cross-Platform Study on Superconducting and Trapped-Ion Processors

Ancilla reuse in repeated syndrome extraction couples reset quality to logical-cycle latency. We evaluate blind reset – unitary-only recycling via scaled sequence replay – on IQM Garnet, Rigetti Ankaa-3, and IonQ under matched seeds, sequence lengths, and shot budgets. Using ancilla cleanliness F_clean=P(|0>), per-cycle latency, and a distance-3 repetition-code logical-error proxy, platform-calibrated simulation identifies candidate regions where blind reset cuts cycle latency by up to 38x under NVQLink-class feedback overhead while maintaining F_clean >= 0.86 for L <= 6. Hardware experiments on IQM Garnet confirm blind-reset cleanliness >= 0.84 at L=8 (1024 shots, seed 42); platform-calibrated simulation for Rigetti Ankaa-3 predicts comparable performance. Architecture-dependent crossover lengths are L* ~ 12 (IQM), ~ 11 (Rigetti), ~ 1 (IonQ), and ~ 78 with GPU-linked external feedback. Two added analyses tighten deployment boundaries: a T1/T2 sensitivity map identifies coherence-ratio regimes, and error-bound validation confirms measured cleanliness remains consistent with the predicted diagnostic envelope. A deployment decision matrix translates these results into backend-specific policy selection.

💡 Research Summary

This paper investigates a measurement‑free ancilla recycling technique called “blind reset,” which uses only unitary operations to return an ancilla qubit to the ground state after each syndrome extraction round. The authors evaluate blind reset on three heterogeneous quantum‑processing back‑ends—superconducting IQM Garnet, Rigetti Ankaa‑3, and trapped‑ion IonQ—under identical experimental conditions (same random seeds, sequence lengths, and shot budgets). The key performance metrics are ancilla cleanliness (F_clean = P(|0⟩)), per‑cycle latency, and a logical‑error proxy derived from a distance‑3 repetition code.

Blind reset works by replaying the exact control sequence that generated an unknown rotation on the ancilla, scaling it globally by a factor λ, and playing it back twice (“scale‑and‑double”). This construction drives the net operation close to the identity, leaving the ancilla in a state with high overlap with |0⟩. The authors derive an analytical envelope (Eq. 3) that separates coherent (λ‑dependent) and incoherent (gate‑error‑dependent) contributions to F_clean, providing a diagnostic bound for simulation validation.

A cross‑platform simulation framework incorporates realistic noise models: platform‑specific T₁, T₂, single‑qubit depolarizing error rates (≈0.1–0.2 %), and gate times (30–40 ns for superconductors, 100 µs for ions). Latency is modeled as T_blind = 2 L t_gate for blind reset, while measurement‑based reset incurs T_meas = t_meas + t_fb + t_prep + t_ext, where t_ext captures external feedback overhead such as NVIDIA’s NVQLink (set to 4 µs in the baseline).

Simulation results show that blind reset achieves a clean‑state probability of ~0.88 for the shortest sequence (L = 4) on IQM and Rigetti, significantly higher than the “no‑reset” baseline (~0.72) and only modestly below measurement‑reset (~0.99). As L increases, F_clean degrades non‑monotonically, reaching ~0.65 at L = 16, reflecting the difficulty of finding an optimal λ for longer sequences. The crossover length L*—where blind reset becomes faster than measurement‑reset while still satisfying a cleanliness threshold (F_clean ≥ 0.86)—is platform‑dependent: L* ≈ 12 for IQM, ≈ 11 for Rigetti, and ≈ 1 for IonQ. When external GPU‑linked feedback is included, L* expands dramatically to ≈ 78, indicating that blind reset is especially advantageous in high‑latency feedback environments.

Hardware experiments on IQM Garnet (L = 8, 1024 shots, seed 42) confirm a measured cleanliness of ≥ 0.84, matching the simulation predictions. Simulated performance for Rigetti Ankaa‑3 suggests comparable results, while IonQ’s long gate times make blind reset viable only for the shortest sequences.

Two supplementary analyses tighten deployment boundaries. First, a T₁/T₂ sensitivity map shows that the ratio (T₁/T₂)·(t_gate)⁻¹ must exceed ~10⁴ for blind reset to remain stable; lower ratios cause rapid cleanliness loss. Second, error‑bound validation uses the analytical envelope to flag any simulation output that lies outside the predicted region, confirming that all measured data stay within the envelope.

Finally, the authors present a deployment decision matrix that takes as input platform latency components, required cleanliness, and external feedback latency, and outputs the preferred reset policy and the corresponding crossover length. The matrix enables real‑time scheduler integration: for IQM and Rigetti, blind reset is recommended for L ≤ 10; for IonQ, measurement‑reset is generally preferable except for single‑gate sequences; and in GPU‑accelerated stacks, blind reset remains optimal up to L ≈ 78.

In summary, blind reset offers a practical, measurement‑free ancilla recycling method that can dramatically reduce QEC cycle latency (up to 38×) while maintaining sufficient ancilla purity for logical error suppression. Its performance is largely platform‑agnostic for short sequences, with the dominant factor being the trade‑off between sequence length and latency overhead. The work provides both theoretical foundations and empirical evidence, along with concrete policy guidelines, paving the way for integration of measurement‑free reset primitives into next‑generation fault‑tolerant quantum computing stacks.