Reconfigurable Low-Complexity Architecture for High Resolution Doppler Velocity Estimation in Integrated Sensing and Communication System

In millimeter wave integrated sensing and communication (ISAC) systems for intelligent transportation, radar and communication share spectrum and hardware in a time division manner. Radar rapidly detects and localizes mobile users (MUs), after which communication proceeds through narrow beams identified by radar. Achieving fine Doppler resolution for MU clutter discrimination requires long coherent processing intervals, reducing communication time and throughput. To address this, we propose a reconfigurable architecture for Doppler estimation realized on a system on chip using hardware software codesign. The architecture supports algorithm level reconfiguration, dynamically switching between low-complexity, high-speed FFT-based coarse estimation and high complexity ESPRIT based fine estimation. We introduce modifications to ESPRIT that achieve 6.7 times faster execution while reducing memory and multiplier usage by 79% and 63%, respectively, compared to state of the art approaches, without compromising accuracy. Additionally, the reconfigurable architecture can switch to lower slow time packets under high SNR conditions, improving latency further by 2 times with no loss in performance.

💡 Research Summary

The paper addresses a critical bottleneck in millimeter‑wave integrated sensing and communication (ISAC) systems for intelligent transportation: the need for long coherent processing intervals (CPI) to achieve fine Doppler resolution, which reduces the time available for data communication. To mitigate this trade‑off, the authors propose a reconfigurable Doppler‑velocity estimation architecture implemented on a Xilinx Zynq MPSoC (quad‑core ARM A53 processing system plus Ultrascale programmable logic). The architecture supports runtime switching between a low‑complexity, high‑speed FFT‑based coarse estimator and a high‑complexity, high‑accuracy ESPRIT‑based fine estimator.

The coarse stage uses a zero‑padded FFT to quickly identify the presence of a target in a range‑azimuth cell. When a target is detected, the fine stage applies a subspace method (ESPRIT) that can resolve closely spaced velocities with far fewer slow‑time samples than FFT. The authors’ key contribution lies in redesigning the ESPRIT pseudo‑inverse computation. Traditional implementations rely on singular‑value decomposition (SVD) of a large ((L‑1)×(L‑1)) matrix, which is resource‑intensive. The proposed low‑complexity version replaces SVD with a direct computation of ((E_2^H E_2)^{-1}) for the small (K×K) matrix (where (K) is the number of targets, typically 2). By using determinant and adjugate calculations, the pseudo‑inverse is obtained with far fewer multiplications. The subsequent eigen‑value extraction is simplified to solving a quadratic equation for the 2×2 case.

Hardware mapping exploits BRAM partitioning for parallel covariance accumulation, Xilinx QR factorization IP for eigen‑vector decomposition, and custom pipelines for matrix slicing, pseudo‑inverse, and eigen‑value calculation. The FFT block uses the built‑in LogiCORE FFT IP, which can be reconfigured on‑the‑fly via AXI‑Lite registers. Algorithm selection and parameter changes (PRI, number of packets, FFT size) are controlled by the ARM processor, which triggers dynamic partial reconfiguration (DPR) or dynamic function exchange (DFX) through the PCAP interface. Data movement between PS and PL is handled by DMA over AXI‑MM, ensuring high throughput.

Experimental results are presented for Rician fading channels (Rician factor 2 dB) across a wide SNR range. The low‑complexity ESPRIT achieves the same root‑mean‑square error (RMSE) as the conventional high‑complexity version while delivering a 6.7× speedup. Memory usage drops by 79 % and multiplier count by 63 % relative to the state‑of‑the‑art ESPRIT/MUSIC implementations. Moreover, when the signal‑to‑noise ratio is high, the system can halve the number of slow‑time packets (i.e., halve CPI), cutting processing latency by a factor of two without degrading velocity resolution.

In summary, the work delivers a flexible, resource‑efficient hardware platform that dynamically balances Doppler resolution against communication latency. By enabling runtime algorithm reconfiguration and by drastically simplifying the ESPRIT core, the proposed architecture makes it feasible to achieve super‑resolution radar sensing in ISAC deployments while preserving high data‑rate communication—a crucial step toward practical intelligent‑transportation, digital‑twin, and industrial‑IoT applications.