Quantum Sequential Circuits

This work introduces and characterizes quantum sequential circuits (QSCs) as a hardware-oriented paradigm for quantum computing, built upon a novel foundational element termed the quantum transistor. Unlike conventional qubit-based architectures, QSCs employ symmetry-protected topological junctions where quantum gates are encoded as Choi states via channel-state duality and activated through bulk measurements, utilizing ebits to realize the functional analog of feedback loops in classical sequential circuits. This framework establishes a universal model for quantum computation that inherently incorporates memory and temporal sequencing, complementing existing combinational quantum circuit model. Our work advances the conceptual bridge towards a quantum von Neumann architecture, underscoring the potential of hybrid and modular design principles for the development of large-scale, integrated quantum information processors.

💡 Research Summary

The paper introduces a hardware‑oriented framework for quantum sequential circuits (QSCs), built around a novel component called the quantum transistor. Unlike conventional qubit‑based architectures that treat quantum gates as instantaneous unitary operations, the quantum transistor stores a gate as a Choi state—a static resource state derived from the channel‑state duality. This stored gate resides in a symmetry‑protected topological (SPT) medium such as a one‑dimensional cluster state or a valence‑bond solid, both of which possess protected edge modes that carry logical qubits. By performing bulk measurements on the SPT medium, the logical information is transferred from the left edge (input) to the right edge (output), thereby “activating” the gate.

A central contribution is the identification of ebits (Bell pairs) as the quantum analogue of feedback loops and memory in classical sequential circuits. An ebit, or a product of ebits, provides the periodic boundary condition required for the bulk system, enabling the output of a gate to be teleported back to its input edge mode. Because the bulk measurement is destructive, each gate is a one‑time operation; however, the authors propose a refresh protocol—re‑preparing the Hamiltonian, re‑entangling edge modes, and regenerating ebits—to make the gate reusable. This mechanism mirrors the way classical flip‑flops store and update state, but it is realized through entanglement and measurement rather than charge storage.

The authors demonstrate that QSCs are universal: by storing a universal gate set (H, S, T, CZ) as Choi states and combining them with combinational quantum circuits, any quantum algorithm can be implemented. They further develop several higher‑level constructions:

1. Quantum Registers – arrays of quantum transistors connected in series, forming shift registers that move quantum data via teleportation.
2. Quantum Finite‑State Machines – circuits whose structure is naturally expressed as matrix‑product states (MPS), with registers acting on the bond space, providing a local model of a quantum Turing machine.
3. Hybrid Circuits – integration of combinational and sequential parts across heterogeneous platforms (photonic, superconducting, trapped‑ion, etc.) by establishing ebits between the two sections.
4. Quantum Pipelines – leveraging the stabilizer formalism to parallelize Clifford operations, collect Pauli by‑products, and apply them before non‑Clifford T‑gates, thereby improving throughput.

The paper also supplies a symbolic language for drawing both combinational and sequential quantum circuits, clarifying how stored gates, edge modes, bulk measurements, and ebits are represented.

While conceptually compelling, the proposal faces significant practical challenges. Realizing large‑scale SPT media with controllable bulk measurements remains experimentally demanding; measurement errors and decoherence could quickly degrade the stored Choi states. Continuous generation and recycling of high‑fidelity ebits for feedback loops demand robust entanglement distribution and error‑correction schemes that are not fully detailed. Moreover, the “quantum transistor” terminology may cause confusion with classical transistors, underscoring the need for standardized hardware interfaces.

In summary, the work offers a fresh perspective on quantum hardware design by embedding memory and feedback directly into the physical substrate. By treating gates as stored states and using entanglement as the looping mechanism, it paves a path toward a quantum von Neumann architecture. If the outlined engineering hurdles—SPT material fabrication, precise bulk measurement, and reliable ebit management—can be overcome, quantum sequential circuits could become a cornerstone of scalable, modular quantum processors.