Intrinsically DRC-Compliant Nanophotonic Design via Learned Generative Manifolds

Inverse design has enabled the systematic design of ultra-compact and high-performance nanophotonic components. Yet enforcing foundry design rules during inverse design remains a major challenge, as optimized devices frequently violate constraints on minimum feature size and spacing. Existing fabrication-constrained approaches typically rely on penalty terms, projection filters, or heuristic binarization schedules, which restrict the accessible design space, require extensive hyperparameter tuning, and often fail to guarantee compliance throughout the optimization trajectory. Here, we introduce a framework for nanophotonic inverse design with intrinsic enforcement of design rules through a generative reparameterization of the design space, restricting optimization to a learned manifold of DRC-compliant geometries. We validate this paradigm by designing representative silicon photonic components including broadband power splitters, spectral duplexers, and mode converters operating across the 1,500-1,600 nm band for both electron-beam lithography and photolithography platforms. Across all devices, the manifold-based formulation reaches state-of-the-art performance metrics with over a 5-fold reduction in computational cost compared to pixel-based representations, while ensuring fabrication-compatible geometries throughout the entire design process. By treating fabrication constraints as a fundamental property of the design representation rather than an external penalty, this work establishes a direct pathway toward broadly applicable, platform-agnostic, and intrinsically DRC-compliant nanophotonics.

💡 Research Summary

Inverse design has become a powerful tool for creating ultra‑compact, high‑performance nanophotonic components, but ensuring that the resulting geometries obey foundry design‑rule‑check (DRC) constraints remains a persistent bottleneck. Conventional approaches address DRC compliance by adding penalty terms, applying spatial averaging and projection filters, or using heuristic binarization schedules. While these methods can eventually produce fabricable devices, they require extensive hyper‑parameter tuning, increase the number of optimization iterations, and still risk violating rules during the search, which hampers convergence and scalability.

In this work the authors propose a fundamentally different strategy: they embed DRC compliance directly into the design representation itself. Instead of optimizing a high‑dimensional pixel‑based permittivity vector x∈X, they introduce a low‑dimensional latent vector z∈Z and a differentiable generator network G(z) that maps z to a geometry G(z) belonging to a learned manifold 𝔊. By construction, every point on this manifold satisfies the minimum feature size, spacing, curvature, and enclosure rules for a given fabrication platform, i.e., 𝔊⊂S where S is the set of DRC‑compliant designs. Consequently, the inverse‑design problem reduces to a simple least‑squares objective in latent space:

  arg min₍z₎ ‖F(G(z)) − y*‖²

where F is an electromagnetic solver (e.g., FDTD) and y* is the target spectral or modal response. No additional regularization for DRC is needed, eliminating the hyper‑parameter burden and guaranteeing compliance at every iteration.

The generator architecture is carefully crafted to enforce manufacturability. Starting from a small grayscale tensor (e.g., 8 × 8), the network performs four cascaded up‑sampling steps (scale factor 1.4 each) followed by three up‑sampling‑convolution blocks with 5 × 5 kernels and decreasing channel counts (32, 16, 1). After each convolution a soft‑max activation is applied; a “modified soft‑max” with a trainable slope schedule gradually sharpens the material boundaries during training. A final morphological closing operation (3 × 3) fills tiny gaps and ensures that any remaining features are larger than the minimum printable size. The non‑differentiable threshold at the end of training is handled with a Straight‑Through Estimator (STE), allowing back‑propagation despite the binary decision.

Training uses a composite loss: (i) a topological DRC loss that penalizes violations of minimum width (ηₑ) and minimum spacing (η_d) via erosion/dilation masks, and (ii) a performance loss computed by differentiable electromagnetic simulation. The topological loss does not explicitly encode area constraints; instead, the up‑sampling and closing layers inherently suppress isolated islands and sub‑minimum holes. Over ~200 epochs the DRC loss drops from ~4 × 10⁻² to ~7 × 10⁻⁶, confirming that the generator reliably produces rule‑compliant layouts.

The authors validate the framework on three representative silicon photonic devices operating in the 1500–1600 nm band:

1. Broadband 1 × 2 power splitter – Designed for both electron‑beam lithography (EBL, 60 nm minimum feature) and conventional photolithography (PL, 150 nm). Measured insertion loss is < 0.8 dB and the splitting ratio is 49.5 % ± 0.5 % across the band.

2. Four‑channel spectral duplexer – Provides 20 nm channel spacing with cross‑talk below –25 dB and total insertion loss < 1.2 dB for both platforms.

3. TE₀→TE₁ mode converter – Achieves 92 % conversion efficiency in a 1.5 µm footprint (EBL) and 89 % for PL.

Across all cases, the manifold‑based approach reduces the number of full‑wave simulations by a factor of ~5.3 compared with a pixel‑based baseline, while delivering equal or superior optical performance. Because every intermediate design lies on the DRC‑compliant manifold, no post‑hoc rule checking is required, effectively eliminating a major source of design turnaround time.

A notable advantage is platform‑agnosticism: by simply adjusting the input resolution to the generator, the same trained network can be reused for different minimum feature sizes, enabling rapid adaptation from EBL to deep‑UV photolithography without retraining from scratch.

The paper concludes that embedding fabrication constraints into the generative representation transforms the ill‑posed inverse‑design problem into a tractable, low‑dimensional optimization that is both faster and more reliable. While the current implementation focuses on minimum width, spacing, and curvature, the authors acknowledge that extending the manifold to incorporate thermal, mechanical, or reliability constraints, as well as multi‑objective formulations, will be essential for full‑scale industrial adoption. Nonetheless, the demonstrated 5‑fold computational speed‑up, guaranteed DRC compliance, and high‑performance device outcomes mark a significant step toward automated, foundry‑ready nanophotonic design.