Error thresholds of toric codes with transversal logical gates

The threshold theorem promises a path to fault-tolerant quantum computation by suppressing logical errors, provided the physical error rate is below a critical threshold. While transversal gates offer an efficient method for implementing logical operations, they risk spreading errors and potentially lowering this threshold compared to a static quantum memory. Available threshold estimates for transversal circuits are empirically obtained and limited to specific, sub-optimal decoders. To establish rigorous bounds on the negative impact of error spreading by the transversal gates, we generalize the statistical mechanical (stat-mech) mapping from quantum memories to logical circuits. We establish a mapping for two toric code blocks that undergo a transversal CNOT (tCNOT) gate. Using this mapping, we quantify the impact of two independent error-spreading mechanisms: the spread of physical bit-flip errors and the spread of syndrome errors. In the former case, the stat-mech model is a 2D random Ashkin-Teller model. We use numerical simulation to show that the tCNOT gate reduces the optimal bit-flip error threshold to $p=0.080$, a $26%$ decrease from the toric code memory threshold $p=0.109$. The case of syndrome error coexisting with bit-flip errors is mapped to a 3D random 4-body Ising model with a plane defect. There, we obtain a conservative estimate error threshold of $p=0.028$, implying an even more modest reduction due to the spread of the syndrome error compared to the memory threshold $p=0.033$. Our work establishes that an arbitrary transversal Clifford logical circuit can be mapped to a stat-mech model, and a rigorous threshold can be obtained correspondingly.

💡 Research Summary

The paper addresses a fundamental question in fault‑tolerant quantum computation: how much does a transversal logical gate degrade the error threshold of a topological code? While transversal gates are attractive because they require few qubits and shallow circuits, they inevitably spread physical errors across code blocks, potentially lowering the threshold compared to a static quantum memory. Existing estimates for transversal circuits have been empirical, relying on specific sub‑optimal decoders, and no rigorous, decoder‑independent thresholds have been established.

To fill this gap, the authors generalize the well‑known statistical‑mechanical (stat‑mech) mapping—originally developed for static quantum memories—to dynamical logical circuits that include transversal gates. They focus on two toric‑code blocks acted on by a transversal CNOT (tCNOT) gate. The analysis proceeds in two stages, each corresponding to a different noise model.

1. Persistent Bit‑Flip Errors (Perfect Syndrome Measurements).
   The authors consider a model where bit‑flip errors occur both before and after the tCNOT, with the total error probability p split evenly into two channels of strength (\tilde p) such that (p = 2\tilde p(1-\tilde p)). Because a CNOT does not commute with X on the control qubit, errors on the control propagate to the target, creating correlated error patterns across the two blocks. By introducing “detectors” that track syndrome information through the gate, the authors identify the set of error cycles C that leave the syndrome unchanged. Mapping these cycles to Ising spin variables yields a two‑dimensional random Ashkin‑Teller (AT) model: two coupled Ising layers with random four‑spin interactions whose signs are dictated by the underlying physical errors. The AT model is a natural extension of the random bond Ising model (RBIM) used for the toric‑code memory.

   Using large‑scale Monte‑Carlo simulations, the authors compute the free‑energy difference between trivial and non‑trivial domain walls. The ordered phase (low p) exhibits a domain‑wall free energy that scales linearly with system size, implying exponentially suppressed logical errors; the disordered phase (high p) yields a finite free energy, corresponding to a non‑zero logical error rate even for infinite code distance. The critical point of the AT model is found at (p_{\text{th}} = 0.080), a 26 % reduction from the memory threshold (p_{\text{mem}} = 0.109). This result is decoder‑agnostic because the mapping directly relates the logical error rate to the thermodynamic free energy.

2. Bit‑Flip Errors with Syndrome Errors.
   When syndrome extraction is noisy (each stabilizer measurement flips with probability q), the mapping for a static toric‑code memory leads to a three‑dimensional random 4‑body Ising model (R4bIM), also known as the random plaquette gauge theory. Incorporating the tCNOT introduces a temporal slice where the gate acts; the authors model this by inserting a planar defect into the 3D lattice, i.e., a layer where the four‑body couplings are altered to reflect the error‑spreading nature of the gate. This results in a 3D random 4‑body Ising model with a plane defect.

   Existing literature provides the confinement transition point for the defect‑free R4bIM at (p^{*}\approx 0.033) (for (p=q)). By consulting numerical studies of the defect‑modified model, the authors estimate a conservative threshold of (p_{\text{th}} \approx 0.028) for the tCNOT‑augmented circuit. This corresponds to at most a 14 % reduction relative to the memory case.

The paper also outlines how the construction generalizes to arbitrary transversal Clifford circuits. For any such circuit, one can define a set of spacetime detectors, derive the corresponding error cycles, and map the resulting probability distribution to an n‑body random Ising‑type model (or a coupled AT model). The critical point of the resulting statistical‑mechanical model then yields a rigorous, decoder‑independent threshold for the logical circuit.

In summary, the authors demonstrate that transversal gates do lower the error threshold of toric codes, but the reduction can be precisely quantified using statistical‑mechanical mappings. The thresholds obtained—(p_{\text{th}}=0.080) for pure bit‑flip errors and (p_{\text{th}}=0.028) when syndrome errors are present—provide concrete, rigorous benchmarks for fault‑tolerant architectures that rely on transversal Clifford operations. The methodology establishes a powerful bridge between quantum error correction and classical statistical physics, opening the door to systematic threshold analyses for a broad class of fault‑tolerant quantum circuits.