A biased-erasure cavity qubit with hardware-efficient quantum error detection

Erasure qubits are beneficial for quantum error correction due to their relaxed threshold requirements. While dual-rail erasure qubits have been demonstrated with a strong error hierarchy in circuit quantum electrodynamics, biased-erasure qubits – where erasures originate predominantly from one logical basis state – offer further advantages. Here, we realize a hardware-efficient biased-erasure qubit encoded in the vacuum and two-photon Fock states of a single microwave cavity. The qubit exhibits an erasure bias ratio of over 265. By using a transmon ancilla for logical measurements and mid-circuit erasure detections, we achieve logical state assignment errors below 1% and convert over 99.3% leakage errors into detected erasures. After postselection against erasures, we achieve effective logical relaxation and dephasing rates of $(6.2~\mathrm{ms})^{-1}$ and $(3.1~\mathrm{ms})^{-1}$, respectively, which exceed the erasure error rate by factors of 31 and 15, establishing a strong error hierarchy within the logical subspace. These postselected error rates indicate a coherence gain of about 6.0 beyond the break-even point set by the best physical qubit encoded in the two lowest Fock states in the cavity. Moreover, randomized benchmarking with interleaved erasure detections reveals a residual logical gate error of 0.29%. This work establishes a compact and hardware-efficient platform for biased-erasure qubits, promising concatenations into outer-level stabilizer codes toward fault-tolerant quantum computation.

💡 Research Summary

Quantum error correction (QEC) is a prerequisite for scalable quantum computing, but its overhead can be dramatically reduced if the physical qubits exhibit a biased noise structure. Erasure qubits, where the dominant error is a detectable leakage out of the logical subspace, already lower the required thresholds compared with generic Pauli errors. A further refinement—biased‑erasure qubits—produces erasures almost exclusively from one logical basis state, enabling even more relaxed thresholds when embedded in tailored codes such as the XZZX surface code.

In this work the authors experimentally realize a hardware‑efficient biased‑erasure qubit using a single three‑dimensional (3D) superconducting microwave cavity. The logical basis is encoded in the vacuum and the two‑photon Fock state, |0_L⟩ = |0⟩ and |1_L⟩ = |2⟩, a special case of the 0N code often called the “02 qubit”. Because photon loss predominantly maps |2⟩ → |1⟩ while the vacuum is essentially immune, the erasure error rate associated with |1_L⟩ exceeds that of |0_L⟩ by a factor of about 265, establishing a strong bias.

A transmon ancilla dispersively coupled to the cavity provides two essential capabilities: (i) quantum‑non‑demolition (QND) photon‑number parity measurements that distinguish the odd‑photon erasure state |E⟩ = |1⟩ from the even‑photon logical subspace, and (ii) the ability to implement logical gates via quantum optimal control (QOC) pulses. Logical state preparation, gate execution, and final readout are all performed with QOC, while mid‑circuit erasure checks are interleaved to flag leakage events in real time.

The logical measurement protocol uses two cascaded parity checks—mod (n, 2) and mod (n, 4)—to resolve the four lowest Fock states (|0⟩, |1⟩, |2⟩, |3⟩). This yields an average logical assignment error of 0.97 % when no mid‑circuit check is performed. When a mid‑circuit erasure detection is inserted, the false‑positive rate (incorrectly flagging an erasure) is 0.22 % and the false‑negative rate (missing an actual erasure) is 0.69 %. Consequently, more than 99.3 % of leakage events are successfully converted into detectable erasures.

The authors quantify the dephasing introduced by each erasure detection by inserting a variable number M of checks into a fixed‑duration echoed sequence. The logical X coherence ⟨X_L⟩ initially improves (because genuine erasures are removed) and then decays linearly with M, revealing a per‑check induced dephasing of 0.26 %. This metric is crucial for assessing the trade‑off between erasure removal and additional Pauli‑type errors.

Idle‑time performance is characterized by repeatedly applying erasure checks while the qubit is stored in |1_L⟩. The survival probability yields an erasure rate γ_erasure ≈ (0.2 ms)⁻¹. After post‑selection on no‑erasure outcomes, the effective logical relaxation rate is γ_int + γ_res ≈ (6.2 ms)⁻¹, and the logical dephasing rate is γ_φ ≈ (3.1 ms)⁻¹. Thus the ratio of erasure to residual errors is 31 for relaxation and 15 for dephasing, demonstrating a robust error hierarchy within the logical subspace.

Gate performance is assessed via interleaved randomized benchmarking (RB) with concurrent erasure detection. The residual logical gate error is 2.9 × 10⁻³ (0.29 %), which is roughly sixteen times smaller than the per‑gate erasure probability. This confirms that the mid‑circuit detection does not significantly degrade gate fidelity.

Overall, the 02 biased‑erasure qubit combines three major virtues: (1) a hardware‑minimal architecture (single cavity + one transmon), (2) a very large erasure bias (≈265), and (3) low logical error rates both during idle periods and gate operations. The demonstrated ability to convert >99 % of leakage into flagged erasures, together with modest detection‑induced dephasing, makes this platform an attractive candidate for concatenation with outer stabilizer codes such as XZZX. In such a concatenated scheme, the effective thresholds for both erasure and Pauli errors are expected to be substantially higher than for conventional erasure qubits, potentially enabling fault‑tolerant quantum computation with far fewer physical resources. Future work will likely focus on scaling to multi‑qubit arrays, integrating real‑time erasure handling into full surface‑code cycles, and exploring further bias engineering to optimize the trade‑off between erasure detection overhead and logical coherence.