Echo Cross Resonance gate error budgeting on a superconducting quantum processor

High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6$%$ to 1.2$%$ as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.

💡 Research Summary

This paper presents a comprehensive error budgeting and mitigation study for the native two‑qubit Echo Cross‑Resonance (ECR) gate on a 32‑qubit superconducting quantum processor, the OQC Toshiko Gen‑1 system. The authors first identify three dominant error sources: (i) incoherent errors arising from qubit relaxation (T₁) and dephasing (T₂e), (ii) control‑qubit leakage caused by off‑resonant driving of the control qubit during the cross‑resonance pulse, and (iii) coherent errors primarily due to the always‑on ZZ interaction and residual single‑qubit drive terms. Using measured T₁ and T₂e values (median 69 µs and 103 µs respectively) they calculate incoherent error probabilities for each ECR gate (250–460 ns duration) to be between 0.3 % and 0.8 %.

Leakage is quantified with an error‑amplification circuit that repeats a Z X(π/4) rotation together with a virtual Z(φ) phase sweep. By preparing the control qubit in |0⟩ or |1⟩, the authors distinguish three leakage channels: Λ₀₁ (|0⟩↔|1⟩), Λ₁₂ (|1⟩↔|2⟩), and Λ₀₂/₂ (two‑photon |0⟩↔|2⟩). Among fifteen examined qubit pairs, three exhibit high leakage (1–2 % per Z X(π/4) pulse), seven show intermediate leakage (0.1–1 %), and five have negligible leakage (<0.1 %). To suppress leakage, they employ Derivative‑Removal‑by‑Adiabatic‑Gate (DRAG) pulse shaping. The DRAG parameter α is set analytically from the detuning between the cross‑resonance drive frequency and the offending transition (α = 1/(2πΔf) for single‑photon transitions, α = 1/(4πΔf) for the two‑photon transition). After applying DRAG, leakage errors drop to the 10⁻⁴ level, and in cases where both Λ₀₂/₂ and another channel coexist, a modest 10‑20 % increase in pulse duration further reduces the two‑photon leakage at the cost of a slight rise in incoherent error—an overall beneficial trade‑off.

Coherent errors are analyzed by expanding the effective Hamiltonian of the cross‑resonance interaction: H/ħ = Ω_ZX Z X + Ω_ZY Z Y + Ω_ZZ Z Z + Ω_IX I X + Ω_IY I Y + Ω_ZI Z I + Ω_IZ I Z. The desired term is Ω_ZX Z X; all others constitute coherent error. Ω_ZY is eliminated by calibrating the drive phase, while Ω_IX and Ω_IY are cancelled by applying a simultaneous target‑qubit drive (cancellation pulse). The persistent Ω_ZZ term, arising from the static capacitive coupling, induces a conditional frequency shift that the echo sequence suppresses only to first order, leaving higher‑order residuals. The authors use a reduced set of quantum process tomography measurements (leveraging the known block‑diagonal structure) to estimate Ω_ZY and Ω_ZZ, then apply compensating Z‑rotations and the cancellation pulse to mitigate them.

Putting all contributions together, the pre‑mitigation error budget attributes roughly 30 % of the total ECR error to incoherent decoherence, 20‑30 % to control‑qubit leakage, and the remainder to coherent ZZ‑related errors. After implementing DRAG leakage suppression and coherent‑error compensation, the average ECR gate error across a 16‑qubit chain drops from 4.6 % to 1.2 %, a 3.7× improvement. The median error improvement is especially pronounced for qubit pairs that originally performed poorly, demonstrating that targeted pulse‑level error suppression can effectively trim the low‑performing tail of gate quality distributions without any additional hardware.

The residual unexplained error (≈0.5 % after mitigation) is hypothesized to stem from time‑varying two‑level system defects, frequency fluctuations not captured by static T₁/T₂e measurements, or measurement noise. The authors suggest that real‑time calibration and further refinement of pulse shaping could address these remaining contributions. Overall, the work showcases a practical, low‑overhead methodology for substantially enhancing two‑qubit gate fidelity on medium‑scale superconducting processors, providing a roadmap for scaling up while maintaining uniform high‑quality operations.