An Energy-Efficient Adiabatic Capacitive Neural Network Chip

Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under stringent energy constraints, especially for battery-powered and edge devices. To address this, we present a mixed-signal adiabatic capacitive neural network chip, designed in a 130$nm$ CMOS technology, to demonstrate significant energy savings coupled with high image classification accuracy. Our dual-layer hardware chip, incorporating 16 single-cycle multiply-accumulate engines, can reliably distinguish between 4 classes of 8x8 1-bit images, with classification results over 95%, within 2.7% of an equivalent software version. Energy measurements reveal average energy savings between 2.1x and 6.8x, compared to an equivalent CMOS capacitive implementation.

💡 Research Summary

Recent advances in artificial intelligence have driven a surge in data‑intensive applications such as video processing and high‑resolution sensing, creating a pressing need for high‑performance computation under tight energy budgets, especially for battery‑powered edge devices. Conventional digital accelerators (SIMD, DSP, GPU) consume substantial dynamic power, and while various analog and mixed‑signal approaches (sub‑threshold CMOS, memristors, capacitive synapses) have been explored, they still suffer from current surges and resistive losses. In this context, the authors present a mixed‑signal adiabatic capacitive neural network (ACNN) chip fabricated in a 130 nm CMOS process that leverages adiabatic logic to dramatically reduce energy dissipation.

Adiabatic operation uses a dedicated Power Clock (PC) that provides a sinusoidal or trapezoidal voltage waveform. By charging and discharging the neural capacitors slowly, the circuit recovers energy back into the supply instead of dissipating the full ½ C V² during each transition. The core computational element, the Adiabatic Capacitive Neuron (ACN), implements two switched‑capacitor trees—one for positive weights and one for negative weights. Input bits control SPDT switches that connect the corresponding weight capacitors to the PC; otherwise the capacitors are grounded. Multi‑input multiply‑accumulate (MAC) operations are performed through charge redistribution and voltage division across the capacitor array. Custom Metal‑Oxide‑Metal (MOM) unit capacitors of approximately 2 fF are tiled to realize the required weight capacitances, while bias and ballast capacitors set neuron bias levels, limit voltage swing, and provide periodic reset. The neuron’s output is generated by a Threshold Logic (TL) comparator that evaluates the differential membrane voltages (v⁺_m vs. v⁻_m) and produces a binary 1‑bit result. Although the TL is powered by a non‑adiabatic DC supply, its high‑impedance nature does not impede energy recovery.

The chip integrates 16 single‑cycle MAC engines arranged in two computational layers, separated by a dedicated Routing Layer (RL). The 64‑bit (8 × 8) binary image inputs are streamed via a 1 MHz SPI interface, deserialized into a parallel bus, and fed to the first ACN layer (12 neurons). The RL contains an adiabatic buffer, a Dynamic Latch‑Clocked Comparator (DLCC), and a latch stage, all driven by a second, phase‑shifted Power Clock (PC₂) that is 180° out of phase with the PC used for the ACN layers (PC₁). This arrangement decouples the layers, synchronizes signal transfer, and enables charge recovery across the two clock domains. The second ACN layer (4 neurons) receives the routed signals and produces a 4‑bit classification output.

For functional validation, the authors trained a TensorFlow software ANN with two hidden layers (12 neurons total) on the “arrows8” dataset (8 × 8 binary images, four directional classes). The software model achieved 98.65 % accuracy. Weight values were directly mapped to ACN capacitances; the mapping is theoretically lossless, but practical quantization errors arise from the 2 fF granularity of the MOM capacitors and parasitic capacitances. Circuit‑level simulations predict a maximum accuracy loss of 0.39 % (to 98.26 %). Experimental measurements on five fabricated chips, each tested over ten repetitions, yielded classification accuracies above 95 % and a deviation of less than 2.7 % from the software baseline.

Energy consumption was measured against an equivalent non‑adiabatic CMOS‑capacitive implementation under identical operating conditions (1 MHz, 1.5 V). The adiabatic ACNN demonstrated average energy reductions ranging from 2.1× to 6.8×, attributable to the gradual voltage ramps of the PC that suppress current peaks and minimize resistive dissipation. The chip occupies a core area of 1.145 mm × 1.307 mm for the computational blocks and measures 1.84 mm × 2.13 mm overall, integrating the MAC engines, routing logic, and external PC generation circuitry on a custom PCB.

In summary, this work showcases the first silicon demonstration of an adiabatic capacitive neural network capable of high‑accuracy inference with substantial energy savings. The architecture is well‑suited for low‑power edge AI, offering a pathway to battery‑friendly intelligent devices. Future directions include extending the approach to multi‑bit weights, deeper network topologies, and on‑chip generation of the power‑clock waveform, which together could further improve both energy efficiency and computational fidelity.