Scaled Ultra-Wide Bandgap AlGaN Polarization-Graded FET with Ultra-thin Buffer Layer

We report on the design and demonstration of ultra-wide bandgap AlGaN polarization-graded field effect transistors with ultra-thin channels to enable excellent current density and high-frequency performance while significantly reducing thermal resistance. We use polarization-graded AlGaN layers and ultra-thin pseudomorphic AlGaN buffer layers to enable low thermal resistance and excellent structural quality. The polarization-graded field effect transistors (PolFETs) demonstrated here show Imax over 800mA/mm and current/power gain cutoff frequency (fT/fmax) of 26/28 GHz. Small signal modeling and analysis were used to determine parasitic/transit delays, and gate-resistance thermometry was implemented to thermally characterize AlGaN PolFET and benchmark against state-of-the-art AlGaN HEMTs. The ultra-thin AlGaN PolFET showed thermal resistance of 12 K.mm/W, representing a significant reduction from typical AlGaN transistors. These results show state-of-art combination of high current density, excellent fT-LG product for ultra-wide bandgap AlGaN transistors, and superior thermal performance, and highlight the promise of AlGaN transistors for future RF and mm-wave applications.

💡 Research Summary

The paper presents a comprehensive approach to overcoming the key challenges of ultra‑wide‑bandgap (UWBG) AlGaN lateral transistors—namely, efficient current injection, field management, and thermal handling—by integrating an ultra‑thin pseudomorphic AlGaN buffer with a polarization‑graded channel. The epitaxial stack, grown by ammonia molecular beam epitaxy on an AlN‑on‑sapphire template, consists of a 300 nm AlN nucleation layer, a 45 nm pseudomorphic Al₀.₅Ga₀.₅N buffer, a 4 nm unintentionally doped spacer, and a 40 nm channel whose Al composition linearly grades from 50 % to 75 %. A Si delta‑doping layer (2.5 × 10²⁰ cm⁻³) is placed at the AlN/AlGaN interface to compensate the negative polarization charge without creating a parasitic electron channel. Structural quality is confirmed by HR‑XRD, reciprocal space mapping (fully strained) and atomic‑force microscopy (RMS roughness 0.134 nm).

Device fabrication employs V/Al/Ti/Au ohmic contacts, rapid thermal annealing, Cl₂‑based RIE mesa isolation, and Ni/Au gates defined by e‑beam lithography. Electrical characterization yields a sheet charge density of 1.86 × 10¹³ cm⁻², electron mobility of 76 cm²/V·s, and a sheet resistance of 4.38 kΩ/□. Transfer‑length measurements give a contact resistance of 4.8 Ω·mm. The PolFET delivers a maximum drain current density exceeding 800 mA/mm at V_GS = +2 V and V_DS = 20 V, a transconductance of ~70 mS/mm, and a threshold voltage of –12 V. Small‑signal S‑parameter analysis shows a current‑gain cutoff frequency (f_T) of 26 GHz and a maximum oscillation frequency (f_max) of 28 GHz for a gate length of 200 nm. Small‑signal modeling extracts a parasitic delay of 3.6 ps (dominated by the relatively high contact resistance) and a transit delay of 3 ps (limited by gate length scaling).

Thermal performance is evaluated using gate‑resistance thermometry (GRT). Calibration of the temperature coefficient of resistance enables direct measurement of self‑heating under bias. The PolFET exhibits a thermal resistance of 12 K·mm/W, a substantial reduction compared with a conventional AlGaN HEMT with a thick buffer (30 K·mm/W). The improvement is attributed to the ultra‑thin AlGaN layers that shorten the heat‑flow path and reduce the thermal conduction resistance.

In conclusion, the authors demonstrate that an ultra‑thin pseudomorphic buffer combined with a polarization‑graded channel and appropriate Si delta‑doping can simultaneously achieve high current density (>800 mA/mm), competitive RF performance (f_T/f_max = 26/28 GHz), and markedly lower thermal resistance (12 K·mm/W). The work establishes a new epitaxial design methodology for UWBG AlGaN transistors, paving the way for high‑power RF and millimeter‑wave applications. Future directions include integrating reverse‑graded contact layers to lower contact resistance and further scaling of gate length to reduce transit delay.