Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: the monolithic stitched sensor (MOSS)

This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026-2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 $\times$ 25.9 cm, thinned to 50 $μ$m. The chip architecture, in-pixel front-end, laboratory and in-beam characterisation, susceptibility to single-event effects, and series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

💡 Research Summary

The paper reports on the design, fabrication, and comprehensive characterization of the first wafer‑scale monolithic stitched sensor (MOSS) developed for the ALICE ITS3 upgrade, scheduled for installation during LHC Long Shutdown 3 (2026‑2030). ITS3 aims to dramatically reduce the material budget of the inner tracking layers to about 0.09 % X₀ per layer by employing ultra‑thin (50 µm) silicon sensors that are bent into true cylindrical half‑barrels. To achieve the required sensor size, the authors used 65 nm CMOS imaging technology on 300 mm wafers together with a stitching process that overcomes the reticle size limitation, allowing a single sensor to reach 1.4 cm × 25.9 cm.

MOSS consists of a left end‑cap (LEC), a right end‑cap (REC), and ten repeated sensor units (RSUs) arranged linearly. Each RSU is split into a top and a bottom half‑unit; the top half contains a 256 × 256 pixel matrix with a 22.5 µm pitch, while the bottom half holds a 320 × 320 matrix with an 18.0 µm pitch. In total the chip hosts roughly 6.72 million pixels, providing a testbed for both high‑density and lower‑density pixel architectures on the same wafer. The stitching backbone carries power, control, and read‑out lines across the entire length of the sensor; power is injected only at the two ends (LEC and REC) to minimise voltage drops, while each half‑unit can be powered and read out independently via dedicated wire‑bond pads.

The in‑pixel front‑end is a low‑power folded‑cascode amplifier with weak‑inversion transistors. Four bias currents (I_bias, I_biasn, I_reset, I_db) and four bias voltages define the operating point. I_bias controls gain and noise, with a typical value that yields a gain sufficient for a signal‑to‑noise ratio above 20 while keeping the average power consumption below 40 mW cm⁻². I_reset is set in the pico‑ampere range, just above the leakage current, to guarantee a stable baseline without adding significant shot noise. A level‑shifter transistor raises the collection diode bias, reducing its capacitance and improving timing.

Laboratory measurements at room temperature and –20 °C demonstrated low leakage currents (< 10 nA cm⁻²), ENC values around 5–7 e⁻ rms, and a power draw of ~35 mW cm⁻². Beam tests confirmed a charge‑collection efficiency above 99 % for 1 MeV n_eq cm⁻² fluences up to 10⁹ n_eq cm⁻², and the sensor remained functional after exposure to the full ITS3 radiation specification (4 kGy TID and 4 × 10¹² n_eq cm⁻² NIEL). Single‑event upset (SEU) cross‑sections were measured at ~10⁻¹² bit cm⁻² s⁻¹, indicating negligible susceptibility in the expected LHC environment.

Yield analysis showed that 99.3 % of the 6.72 M pixels operated correctly. The few failures were localized near stitching boundaries, where increased metal resistance and occasional connectivity defects were observed. These issues are attributed to design‑for‑manufacturability (DfM) constraints and can be mitigated by adjusting metal thickness and improving stitch alignment tolerances.

Overall, MOSS validates the feasibility of wafer‑scale stitched MAPS for the ITS3 concept. It meets all critical specifications: ultra‑low material budget, high granularity, low power consumption, and radiation hardness. The work provides a detailed roadmap for scaling up to full‑size cylindrical half‑barrels, including recommendations for production yield optimisation, thermal management (air cooling is viable due to low power), and integration with the ALICE read‑out architecture. Future steps will focus on mass production, system‑level integration tests, and further optimisation of the front‑end to push noise below 5 e⁻ while maintaining the stringent power budget.