An End-to-End Neural Network Transceiver Design for OFDM System with FPGA-Accelerated Implementation

The evolution toward sixth-generation (6G) wireless networks demands high-performance transceiver architectures capable of handling complex and dynamic environments. Conventional orthogonal frequency-division multiplexing (OFDM) receivers rely on cascaded discrete Fourier transform (DFT) and demodulation blocks, which are prone to inter-stage error propagation and suboptimal global performance. In this work, we propose two neural network (NN) models DFT-Net and Demodulation-Net (Demod-Net) to jointly replace the IDFT/DFT and demodulation modules in an OFDM transceiver. The models are trained end-to-end (E2E) to minimize bit error rate (BER) while preserving operator equivalence for hybrid deployment. A customized DFT-Demodulation Net Accelerator (DDNA) is further developed to efficiently map the proposed networks onto field-programmable gate array (FPGA) platforms. Leveraging fine-grained pipelining and block matrix operations, DDNA achieves high throughput and flexibility under stringent latency constraints. Experimental results show that the DL-based transceiver consistently outperforms the conventional OFDM system across multiple modulation schemes. With only a modest increase in hardware resource usage, it achieves approximately 1.5 dB BER gain and up to 66% lower execution time.

💡 Research Summary

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The paper addresses the growing demand for high‑performance transceiver architectures in upcoming 6G wireless networks by fundamentally redesigning the core processing blocks of an orthogonal frequency‑division multiplexing (OFDM) system. Conventional OFDM receivers consist of a cascade of modules—synchronization, channel estimation, equalization, demodulation—each optimized locally. This pipeline suffers from error propagation and limited adaptability, especially in the discrete Fourier transform (DFT)/inverse DFT (IDFT) stage, which is traditionally implemented with fixed‑size FFT cores that are rigid and resource‑intensive when dynamic sub‑carrier configurations are required.

To overcome these limitations, the authors propose two lightweight neural‑network (NN) models: DFT‑Net and Demod‑Net. DFT‑Net replaces both the IDFT at the transmitter and the DFT at the receiver. It learns a complex‑to‑complex mapping by decomposing the complex input into real and imaginary parts, applying four linear layers (real‑weight and imaginary‑weight), batch normalization, and a 1‑D convolutional mixing layer. This architecture mimics the mathematical structure of the DFT matrix while allowing the weights to be optimized from data. Demod‑Net replaces the conventional soft demodulator, converting frequency‑domain symbols into soft‑bit probabilities. It is built from fully‑connected layers with non‑linear activations and is trained to adapt to multiple modulation formats (QPSK, 16‑QAM, 64‑QAM) and varying channel conditions.

Both networks are trained end‑to‑end (E2E) using a bit‑error‑rate (BER) loss function. Training data encompass a wide range of channel impairments (multipath fading, Doppler shift, interference, noise) and dynamic sub‑carrier allocations, ensuring robustness. Crucially, the authors enforce operator equivalence: the NN inputs and outputs retain the same tensor shapes and data formats as the traditional blocks, enabling seamless hybrid deployment where legacy FFT or demodulation modules can be swapped in or out without redesigning the surrounding system.

Recognizing that inference‑heavy NNs are often unsuitable for real‑time radio‑frequency processing, the paper introduces a custom FPGA accelerator called the DFT‑Demodulation Net Accelerator (DDNA). DDNA maps the two NNs onto a Xilinx Zynq UltraScale+ SoC using fixed‑point (16‑bit) arithmetic. The accelerator exploits block matrix multiplication, data merging, and a fully pipelined execution schedule to achieve high parallelism and low latency. A unified AXI interconnect provides compatibility with the SoC’s processing system, allowing the NN inference to run alongside traditional baseband functions. Compared with generic data‑processing units (DPUs) and commercial FFT IP cores, DDNA delivers higher throughput (over 2× for N=128) while consuming only modest additional LUT, FF, and DSP resources (≈10 % increase) and maintaining power consumption below 1 W.

Experimental results are presented at three levels. Algorithmic performance shows that the NN‑based transceiver consistently outperforms the conventional FFT‑plus‑soft‑demodulator chain across all tested modulation schemes, achieving an average 1.5 dB BER gain. Hardware evaluation demonstrates that DDNA reduces overall OFDM frame processing latency by up to 66 %, meeting stringent real‑time constraints. Resource utilization analysis confirms that the accelerator’s flexible architecture can accommodate varying DFT sizes without the need for redesign, unlike static FFT IP cores that require separate configurations for each size. Finally, hybrid deployment experiments—where only one of the two NN blocks is used—still retain most of the BER improvement while further limiting resource usage, validating the operator‑equivalence design principle.

The paper’s contributions are threefold: (1) a jointly optimized E2E NN replacement for DFT/IDFT and demodulation that mitigates inter‑module error amplification; (2) a hardware‑aware NN design that balances accuracy, latency, and resource consumption, together with a dedicated FPGA accelerator that leverages the parallel nature of matrix operations; (3) a comprehensive evaluation framework that spans algorithmic metrics, model complexity, and on‑chip verification, establishing the practicality of deep‑learning‑based physical‑layer components for future wireless systems.

Future work is outlined to extend the approach to larger transform sizes, multi‑antenna (MIMO) scenarios, model compression techniques (pruning, quantization, knowledge distillation), and over‑the‑air (OTA) testing on real‑world channels. The authors also suggest exploring standardization pathways for integrating neural‑network‑based PHY blocks into emerging 6G specifications.

In summary, the study demonstrates that carefully crafted, lightweight neural networks can replace fundamental OFDM processing blocks, delivering measurable BER improvements and latency reductions while remaining implementable on reconfigurable hardware such as FPGAs. This paves the way for more adaptable, AI‑driven physical‑layer designs in next‑generation wireless communications.