Automated Synthesis of Safe Digital Controllers for Sampled-Data Stochastic Nonlinear Systems

We present a new method for the automated synthesis of digital controllers with formal safety guarantees for systems with nonlinear dynamics, noisy output measurements, and stochastic disturbances. Our method derives digital controllers such that the corresponding closed-loop system, modeled as a sampled-data stochastic control system, satisfies a safety specification with probability above a given threshold. The proposed synthesis method alternates between two steps: generation of a candidate controller pc, and verification of the candidate. pc is found by maximizing a Monte Carlo estimate of the safety probability, and by using a non-validated ODE solver for simulating the system. Such a candidate is therefore sub-optimal but can be generated very rapidly. To rule out unstable candidate controllers, we prove and utilize Lyapunov’s indirect method for instability of sampled-data nonlinear systems. In the subsequent verification step, we use a validated solver based on SMT (Satisfiability Modulo Theories) to compute a numerically and statistically valid confidence interval for the safety probability of pc. If the probability so obtained is not above the threshold, we expand the search space for candidates by increasing the controller degree. We evaluate our technique on three case studies: an artificial pancreas model, a powertrain control model, and a quadruple-tank process.

💡 Research Summary

The paper introduces a novel automated synthesis framework for digital controllers that provide formal safety guarantees for sampled‑data stochastic nonlinear systems (SDSS). Such systems consist of a continuous‑time nonlinear plant subject to random disturbances and noisy measurements, together with a digital controller that samples the plant output at a fixed period τ and holds the control input constant between samples. The controller is parameterised by a finite set of coefficients (the “controller degree” L and the associated a_i, b_i coefficients), which are the synthesis targets.

The core contribution is an iterative two‑stage algorithm that alternates between rapid candidate generation and rigorous verification. In the candidate generation step (procedure optimize), a Monte‑Carlo estimate of the safety probability is maximised using a non‑validated ODE solver. This fast simulation yields a sub‑optimal controller p_c quickly, but may be inaccurate. To prune obviously bad candidates, the authors prove a Lyapunov indirect‑method‑based instability condition for sampled‑data nonlinear systems: if the linearised closed‑loop system (obtained by Jacobian linearisation around the equilibrium) has any eigenvalue outside the unit circle, then the original nonlinear closed‑loop system cannot be Lyapunov stable, and therefore cannot satisfy the required input‑to‑state stability (ISS) property. This necessary condition is cheap to check and eliminates unstable designs early.

In the verification step (procedure verify), a validated solver based on Satisfiability Modulo Theories (SMT) is employed. It computes a statistically sound confidence interval