Low Power Artificial Neural Network Architecture

Recent artificial neural network architectures improve performance and power dissipation by leveraging resistive devices to store and multiply synaptic weights with input data. Negative and positive synaptic weights are stored on the memristors of a reconfigurable crossbar array (MCA). Existing MCA-based neural network architectures use high power consuming voltage converters or operational amplifiers to generate the total synaptic current through each column of the crossbar array. This paper presents a low power MCA-based feedforward neural network architecture that uses a spintronic device per pair of columns to generate the synaptic current for each neuron. It is shown experimentally that the proposed architecture dissipates significantly less power compared to existing feedforward memristive neural network architectures.

💡 Research Summary

The paper introduces a low‑power feed‑forward artificial neural network (ANN) architecture that combines a reconfigurable memristive cross‑bar array (MCA) with a spintronic domain‑wall (DW) device acting as an interface module (IM) for each neuron. Traditional MCA‑based neural networks store positive and negative synaptic weights using pairs of memristors, but they rely on either high‑power voltage converters (dual‑row designs) or operational amplifiers per column (dual‑column designs) to sum the column currents and generate the total synaptic current for each neuron. These auxiliary circuits dominate the power budget and limit scalability.

In the proposed architecture, each neuron is assigned a pair of MCA columns (one for positive contributions, one for negative). The currents flowing through the positive and negative columns, I⁺ and I⁻, are fed into a three‑terminal DW spintronic device. The IM operates under three non‑overlapping clocks:

1. Reset (Clk1) – the DW is centered, setting the device to its low‑resistance state (R_L).
2. Write (Clk2) – the difference I⁺ − I⁻ is injected, moving the domain wall and changing the resistance to a value proportional to the net synaptic current.
3. Read (Clk3) – a current‑mirror converts the resistance‑dependent voltage into a signal that drives a conventional analog activation circuit (e.g., a sigmoid implemented in