Indicating Asynchronous Multipliers

Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of indicating asynchronous multipliers, which are inherently elastic and are robust to timing, process, and parametric variations, and are modular. We consider the physical implementation of many weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by adopting the array multiplier architecture. The multipliers are synthesized in a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols are considered for the data communication. The multipliers are realized using strong-indication or weak-indication full adders. Strong-indication 2-input AND function is used to generate the partial products in the case of both RTZ and RTO handshaking. The full adders considered are derived from different indicating asynchronous logic design methods. Among the multipliers considered, a weak-indication asynchronous multiplier utilizing the biased weak-indication full adder is found to be efficient in terms of the cycle time and the power-cycle time product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO handshake protocol is found to be preferable than the 4-phase RTZ handshake protocol for achieving enhanced optimizations in the design metrics.

💡 Research Summary

The paper investigates the physical implementation of indicating asynchronous multipliers using a 32/28‑nm CMOS technology. The authors adopt a 4×4 array multiplier architecture and explore both 4‑phase return‑to‑zero (RTZ) and return‑to‑one (RTO) handshake protocols for data communication. Fourteen different multiplier variants are realized: three strong‑indication full‑adder designs and four weak‑indication full‑adder designs, each instantiated under both RTZ and RTO protocols, yielding a total of fourteen implementations.

The core of an indicating asynchronous circuit is its dual‑rail data encoding and the use of C‑elements for completion detection. In RTZ, a spacer is represented by both rails being low (0,0) and data by a single high rail; in RTO the spacer is (1,1) and data is the complement of the RTZ encoding. Completion detection for RTZ uses OR gates followed by C‑elements, while RTO uses AND gates followed by C‑elements. The forward latency (time to process data) and reverse latency (time to process the spacer) together define the cycle time, analogous to a clock period in synchronous designs.

Strong‑indication circuits wait for all primary inputs before producing any output, leading to worst‑case forward and reverse latencies that dominate the cycle time. Weak‑indication circuits can produce all but one output after a subset of inputs, only completing the final output when the last input arrives. This data‑dependent behavior can reduce average cycle time, area, and power, especially when the underlying full‑adder cells are themselves weak‑indicating.

For the multiplier, sixteen 2‑input AND gates generate the partial products, and twelve full adders sum them. The AND gates are implemented as strong‑indication cells for both protocols. The full adders are taken from prior work: strong‑indication designs from references