A Neuron Based Switch: Application to Low Power Mixed Signal Circuits

Human brain is functionally and physically complex. This ‘complexity’ can be seen as a result of biological design process involving extensive use of concepts such as modularity and hierarchy. Over the past decade, deeper insights into the functioning of cortical neurons have led to the development of models that can be implemented in hardware. The implementation of biologically inspired spiking neuron networks in silicon can provide solutions to difficult cognitive tasks. The work reported in this paper is an application of a VLSI cortical neuron model for low power design. The VLSI implementation shown in this paper is based on the spike and burst firing pattern of cortex and follows the Izhikevich neuron model. This model is applied to a DC differential amplifier as practical application of power reduction

💡 Research Summary

The paper presents a novel low‑power design methodology that leverages a biologically inspired spiking neuron model to control the power supply of an analog mixed‑signal circuit. Using the Izhikevich cortical neuron model, the authors implement a VLSI neuron in 0.35 µm CMOS technology. The neuron circuit consists of 14 MOSFETs that emulate the integrate‑and‑fire dynamics through equivalent resistive and capacitive behavior realized with MOSFET transistors, thereby avoiding the area and power penalties of discrete capacitors and resistors. The circuit can generate a variety of firing patterns—regular spiking, intrinsic bursting, chatter, fast spiking—by adjusting bias voltages and transistor dimensions (M4, M6, M7).

The neuron’s output spikes are used to drive two MOSFET switches (S1 and S2) that gate the power rails of a differential amplifier. A high‑amplitude pulse turns the switches ON, while a low‑amplitude pulse turns them OFF. By configuring the pulse duty cycle to 1 % and the spike frequency to 10 MHz, the amplifier is active for only 1 % of each cycle, resulting in a theoretical static power reduction of approximately 99 % compared with a continuously powered design. Dynamic power during the ON phase is modeled as the charging and discharging of the equivalent MOSFET capacitances, while static power in the OFF phase is essentially zero except for leakage. The authors derive analytical expressions for P_ON and P_OFF, showing that total power scales linearly with the number of switches (6 + n) in the circuit.

The paper also discusses practical considerations such as the impact of high‑frequency switching on the amplifier’s slew rate, the need for buffer stages or cascaded amplifiers to mitigate parasitic capacitance, and the scalability of the approach to more complex circuits (memory cells, signal‑processing blocks, image‑processing pipelines). By using the neuron’s intrinsic high‑frequency spiking, the design achieves rapid on/off transitions without sacrificing performance, and the neuron model itself provides a flexible platform for generating diverse control waveforms.

Overall, the work demonstrates that a cortical‑neuron‑based power‑switch can dramatically lower the average power consumption of mixed‑signal circuits while preserving functional integrity, offering a promising avenue for energy‑efficient ASIC and system‑on‑chip designs.