AIG Rewriting Using 5-Input Cuts

1 AIG Re writing Using 5-Input Cuts Nan Li Elena Dubrova Royal Institute of T echnology , ES/ICT/KTH, 164 46 Kista, Sweden Abstract —Rewriting is a co mmon approach to logic opti miza- tion based on local transf ormations. Most commer cially a vailable logic synthesis tools include a rewriting engine that may be used multiple times on the same netlist during optimization. This paper presents an And -In verter graph based rewriting algorithm using 5-input cuts. The best cir cuits are pr e-computed f or a subset of NPN classes of 5-variable fu nctions. Cut enu meration and Boolean matching are used to identi fy r eplacement candid ates. The presented appr oach is expected to com plement existing rewriting approaches which are usually based on 4-input cu ts. The experimental results show that, b y addin g the new rewriting algorithm to ABC synthesis tool, we can further reduce the area of heavily opti mized large circuits by 5.57% on avera ge. Index T er ms —Logic optimization, rewriting, NPN classes, cu t enumeration, Boolean matching I . I N T RO D U C T I O N Logic optimization approac hes can be divided into algorithmic-b ased meth ods , which ar e based on glob al trans- formation s, an d rule-ba sed methods , wh ich are b ased on local transform ations [1]. Rule-based methods, also called r ewr iting , use a set of rules which are applied when certain pattern s are found . A r ule transfo rms a pattern fo r a local sub-expression, or a sub-circuit, in to another equiv alen t o ne. Since r ules need to be described , an d hen ce the ty pe available o f op er- ations/gates must be known, th e r ule-based approac h usually requires that the description of the logic is confined to a limited number o f operatio n/gate types such as AND, OR, XOR, NO T etc. In add ition, the tran sformation s have limited o ptimization capability since they ar e local in nature. Examples of r ule- based systems include LSS [2] and SOCRA TES [3]. Algorithmic methods use g lobal transforma tions su ch as decomp osition or f actorization, and therefor e they are much more p owerful com pared to the ru le-based m ethods. However , general Boo lean m ethods, in cluding don ’t care op timization, do no t scale well fo r large fu nctions. Algeb raic metho ds are fast and robust, but they are n ot complete and thus often giv e lower q uality results. For this reason s, indu strial logic synthesis systems norm ally use alge braic r estructuring methods in a combinatio n with rule-b ased meth ods. In this p aper, we pro pose a new rewriting alg orithm based on 5 -Input cu ts. In the algorithm , th e b est circuits are pre- computed for a subset o f NPN cla sses of 5-variable fu nctions. Cut enum eration techniq ue [ 4] is used to find 5-in put cuts for all nod es, and some o f them are replaced with a b est circuit. The Boolean matcher [5] is u sed to map a 5-inpu t fun ction to its c anonical form. Th e p resented approach is expected to compleme nt existing rewriting approach es which are usua lly based on 4-input cuts. Ou r experimental results show that, by adding the new r ewriting algorith m to ABC synthesis tool [6], we can fur ther red uce the area of heavily optimized large circuits by 5.57% on a verage. The p aper is organized as follows. Section II describes main n otions a nd definition s used in the sequel. Section III summarises previous work. Section IV presents the p roposed approa ch. Section V shows exp erimental resu lts. Section VI conclud es the paper and discusses open problems. I I . B AC K G RO U N D A Boo lean ne twork is a directed acyclic g raph, of which the nodes represent logic gates, a nd the directed edges represen t connectio ns of the gate s. A n etwork is also referred to as a cir cuit . A node of the ne twork h as zero or more fanins , and zero or more fa nouts . A fa nin of a node n is a no de n in such th at th ere exists an edge fr om n in to n . Similarly , a fan out of a no de n is a n ode n out such that there is an edg e fro m n to n out . The primary inp uts (PIs) o f a network are the zero-fanin nodes of the network. Th e primary outpu ts o f a network are a subset of all no des. If a network contain s flip-flops, the inpu ts/outputs of the flip-flops a re treated as POs/PIs of the network. An An d-Inverter gr aph (AIG) is a network , of which a node is either a PI or a 2-inp ut AND gate, an d an edge is n egatable. An AI G is structurally hashed [7] to ensu re u niqueness o f the nodes. The a r e a o f an AIG is me asured b y the numbe r of nodes in the network. A cut of a n ode n is a set C o f nodes such that any path from a PI to n mu st pass thro ugh at least o ne nod e in C . Node n itself forms a trivial cut . The nodes in C are ca lled the l eaves of cu t C . A cut C is K -feasible if | C | ≤ K ; a dditionally , C is called a K - input cut if | C | = K . The level of a node n is the numbe r of edges of th e lon gest path f rom any PI to n . The depth of a network is the largest lev el am ong a ll internal nodes o f the network. T wo Boole an functio ns, F and G , are NPN-equiva lent and belong to the same NPN equ ivalence class , if F can be tran s- formed into G thro ugh negation o f inputs (N), per mutation of inputs (P), and negation of the outpu t (N) [8]. I I I . P R E V I O U S W O R K Re writing o f n etworks was introduc ed in th e ea rly logic synthesis systems. SOCRA TES [3] and the IBM system [2][9] perfor med rewriting un der a set of rewriting ru les to replace a comb ination of library g ates with ano ther co mbination of gates which had a smaller area or delay . In SOCRA TES, these ru les were manag ed in an expert system decidin g which ones to apply and wh en. The r ules in SOCRA TES were written b y h uman design ers, based on p ersonal exper ience and observation of experimental results. 2 In the MIS system [10], which later de veloped in to SIS [11], local tra nsformatio ns such as simplifi cation were used to lo- cally optim ize a m ulti-level network a fter glob al o ptimization. T wo-level minimization method s such as ESPRESSO [ 1] were used to min imize the function s associated with the nodes in the network. Similar methods [12] were also included in works of [13][14][15]. Rule-based rewriting metho d was u sed to simp lify AND- OR-XOR networks in the multi-level syn thesis approach pr e- sented in [16]. AIG-based rewriting techn ique presented in [17] i s used as a way to comp ress c ircuits befo re fo rmal verification. Rewriting is perf ormed in two steps. I n the first step , which h appens only once whe n the pr ogram starts, all two-le vel AIG subgr aphs are pre-com puted and stored in a table by their Boolean fu nctions. In the second step, the AIG is traversed in topolo gical order . The two-lev el AIG subgraph s of each n ode are found and the func tionally e quiv alent pre-comp uted subgraph s ar e tried as th e imp lementation of th e no de, while logic sharing with existing nod es is consider ed. T he subgrap h leadin g to least number of overall nodes is used as the r eplacement of the original subgraph . An improved AIG rewriting techn ique for pre-map ping optimization is presented in [ 18]. It u ses 4- input cuts instead of two-level sub graph s in rewriting, and pr eserves the n umber of log ic levels so the area is red uced without in creasing delay . Additionally , AIG balancing , which min imizes delay without in creasing ar ea, is used toge ther with rewriting, to achieve better results. Iterating these tw o processes forms a new technolo gy-ind ependent optimizatio n flow , which is implemented in the sequ ential logic synthe sis an d verification system, ABC [6]. Ex perimen ts show that this implemen tation scales to very large d esigns and is muc h faster tha n SI S [11] and MVSIS [ 19], while r esulting in circuits with the same or better quality . I V . A I G R E W R I T I N G U S I N G 5 - I N P U T C U T S The presented algorithm can be divided into two parts: 1) Best circuit g eneration 2) Cut en umeration and replacement Part 1 of the algor ithm tries to find the optim al cir cuits for a subset of “practical” 5-variable NPN classes, and stores these circuits. Part 2 of the algorithm enumerate s all 5 -input cuts in the target circuit, and ch ooses to replaces a cut with a suitable best circuit. In the impleme ntation of re writing using 4-input cuts in [18], p re-comp uted tables of c anonical forms and the transform ations are kept for all 2 16 4-inpu t fu nctions [ 6][18]. As we extend r ewriting to 5-inpu t cuts, the size of the se tab les becomes 2 32 . i.e. too large for using in a progr am th at runs on a r egular co mputer . In our imp lementation, we u se a Boole an matcher [5] to d ynamically ca lculate the canonica l fo rm o f a tr uth tab le and th e corr espondin g transfo rmation from the original truth table. A. Best cir cuit generation Similarly to [18], we p re-comp ute the c andidate cir cuits for each NPN class so they can be d irectly u sed later . There are 61612 6 NPN equiv alence classes fo r 5-inp ut fun ctions, among which only 2 749 classes app ear in all IWLS 2005 benchm arks [2 0] as 5- feasible cuts. W e picked 1185 o f them with m ore tha n 2 0 occurren ces, and generated best circuits for representative fu nctions o f these classes. Due to the expande d comp lexity o f the prob lem, we h ad to make some tra de-offs betwe en the q uality of the circuits an d the time and memory usage o f our algo rithm. Our impleme n- tation has following differences comp ared to [18]: • Use of Boolean ma tcher to calcu late cano nical form, instead of table look-u p. • Use o f a hash map to s tore the candidate into best circuits, instead of using a full table. • Whe n decidin g wh ether to store a no de in th e node list, a node with the same cost as an existing node is discarded , instead of being stored in the list. • No des of b oth canonical function s and the complem ent of the canonical fun ctions are used as the candidate circu it, while in [18] complem ent function s are no t used . • Whe n the num ber of no des r eaches an upper limit, a reduction proced ure is perfor med before the generation continues, leaving only the node s used in the circuit table. W e use two structures to stor e the best c ircuits: the for est , list of all no des, an d the table , storing on ly the po inters to the n odes in the list, which rep resent canon ical functio ns or their complem ents. In the for est , a n ode can either be an AND node or an XOR node, and two incom ing edges of a n ode have compleme ntation attributes. The cost of a node is the number of AND n odes plus twice the numb er of XOR nod es th ose a re reachable from this node tow ards th e in puts. First, the constan t zero node and five nodes for sing le variables are adde d in to the for est . The co nstant no de a nd on e of the variable nod es are add ed to the table , since all variable nodes are NPN equiv alent. Th en, for each p air o f nod es in the for est , fiv e typ es of 2-in put gates are cr eated, using the pair as inputs: • AND g ate • AND g ate w ith first input compleme nted • AND g ate w ith second input complemen ted • AND g ate w ith both inputs complem ented • XOR gate A newly created no de is stor ed in the for est if the following condition s are met, otherwise it is discarded: • T he cost of the node is lower than any other n ode w ith the same func tionality . • T he cost of th e n ode is lower than or e qual to any other node with NPN-equiv alent fu nctionality . In a ddition, th e pointer to this nod e is add ed to the tab le if the following conditio n is also met: • T he fun ction of the n ode is the canonical form rep resen- tati ve, or its co mplement, in the NPN-equiv alence class it belon gs to. When the numb er of nodes in the forest reaches an upp er limit, a n ode redu ction pro cedure is perf ormed, wh ere only the r eachable n odes f rom the n odes in the tab le are left in the for est . 3 Algorithm 1 Genera teBes tCircu its ( P , u , n max ): Generate candidate be st circu its for a subset of NPN classes of 5-in put Boolean function s. 1: Add constant zero nod e to N and C 2: Add variable n odes to N 3: Add node of variable 0 to C 4: for each i fro m 2 to | N | do 5: for each j fro m 1 to i − 1 do 6: TryNod e (AND, N i , N j ) 7: TryNod e (AND, Not ( N i ), N j ) 8: TryNod e (AND, N i , Not ( N j )) 9: TryNod e (AND, Not ( N i ), Not ( N j )) 10: TryNod e (XOR, N i , N j ) 11: if num. of u ncovered practical NPN classes ≤ u t hen 12: return 13: end if 14: if | N | > n max then 15: Reduce Nodes () 16: i ← 1 17: break 18: end if 19: end f or 20: end for The algorithm stops when th e numbe r of uncovered “prac- tical” classes is smaller than a threshold v alue. Finally , the gene rated best circu its are stored, so they can be used later when rewriting takes place. The pseudo- code of the proposed best circu it generation algorithm is shown in Algorithm 1. The Genera teBes tCircu its proced ure retu rns a node list N an d a table of n odes C rec ording the candid ate b est c ircuits for a subset o f NPN classes. It takes three par ameters. Parameter P is a set of tr uth tab les of “prac tical” 5-variable function s. This set co ntains about 12 00 5 -input canon ical NPN representatives with 20 or more occu rrence in I WLS 2005 benchm arks. Parameter u is an integer ind icating the acceptable number of unc overed practical NPN classes; n max is an in teger indicatin g th e lim it number o f n odes whe n a node redu ction is neede d. In o ur implementatio n, u is set to 60, and n max is set to 1000 0000 . The p seudo-co de f or p rocedur e TryNod e is shown in Al- gorithm 2. TryNod e creates a nod e, and determin es whether to put it in to the nod e list and the circu it table. Parameter T ∈ { AND , XOR } indicates whether the new gate shou ld be an AND gate o r an XOR gate. Parameter n 0 and n 1 are two fanins o f th e new gate. Procedur e Reduce Nodes reduces the no de list by rem oving the nodes that are not used in any circu it in th e cir cuit table. Procedur e Canoni caliz e calculates the cano nical form of the truth table of a giv en fu nction. In the alg orithms, variables N , C and M are g lobally accessible. N deno tes the list of all no des. C is a hash map of the cand idate cir cuits; each o f its entry is a set of n odes storing the roo t node of candida te circuits fo r the NPN class of this entry . M is a tem porary hash map to store th e cu rrently minimum costs of all functions. Algorithm 2 TryNod e ( T , n 0 , n 1 ): Create a n ode o f type T with fanins n 0 and n 1 , and determ ine wh ether to put it in to N or C . 1: n new ← Create Node ( T , n 0 , n 1 ) 2: t ← GetTru th ( n new ) 3: if M t not exist o r M t > Cost ( n new ) then 4: M t ← Cost ( n new ) 5: else 6: return 7: end if 8: t canon ← Canoni caliz e ( t ) 9: if ∃ n ∈ C t canon such that Cost ( n ) < Cost ( n new ) then 10: return 11: end if 12: add n new to the end of list N 13: if t 6 = t canon and t 6 = Comple ment ( t canon ) then 14: return 15: end if 16: if ∃ n ∈ C t canon such that Cost ( n ) > Cost ( n new ) then 17: C t canon ← / 0 18: end if 19: if t = t canon then 20: C t canon ← C t canon S { n new } 21: else 22: C t canon ← C t canon S { Not ( n new ) } 23: end if 24: return B. Cut enumeration a nd r ep lacement W e u se a qu ite similar cut enu meration an d replacemen t technique as in [18]. Th e m ain difference is tha t we use a Boolean match er to calculate the c anonical fo rm of the NPN representative as we ll as the tr ansforma tion to the canon ical form from the orig inal fu nction, while in [18], a faster table look-u p is used. The Boolean matcher pro posed in [5] calculates only the canonical form repr esentation. W e modified the program so it can simu ltaneously gen erate the NPN transfo rmation, which is needed wh en co nnecting the replacement g raph to the whole circuit. Nodes are traversed in topolog ical o rder . For each nod e starting from the PIs to the POs, all of its 5 -input cuts are listed [4]. The can onical for m truth table and the correspon d- ing NPN transform ation of each c ut are calculated using the Boolean m atcher [5]. Each cut is then evaluated whether there is a suitab le replacemen t that does no t increase the area of the network. Finally , the cut with the gr eatest g ain is replaced by a best circu it. In th e presented algorith m, zero- cost replacem ent is accepted , since it is a useful app roach for re-arran ging AIG structure to create more opp ortunities in subsequen t rewriting [17]. The pseu do-cod e of the rewriting pro cedure is shown in Algorithm 3 . For each node in th e n etwork, N best denotes th e largest numb er o f nod es saved b y rep lacing a cut of the node by a pre-co mputed cand idate circuit; c best and u best denotes the correspo nding candidate circuit and the original cut, re- spectiv ely . These thre e variables are up dated simultaneou sly , 4 if there exists a p ossible r eplacemen t. Procedur e Connec tToLe aves ( N , c , u , T rans ) con nects the fanins of candid ate c ircuit c to the leaves o f cut u , fo llowing the NPN transfor mation T rans . Procedur e Refere nce ( N , c ) increases th e refer ence count of th e no des belon g to su b-circuit c , in network N , whe reas Derefe rence ( N , c ) decr eases the r eference coun t. When the referenc e cou nt of a n ode beco mes zero, the nod e does n ot belong to the network. Algorithm 3 Rewrit eNetw ork ( N , C ): Re write a Boolean network N using candidate circuits sto red in hash map C . 1: for each nod e n in N , in topo logical orde r do 2: N best ← − 1 3: c best ← NULL 4: u best ← NULL 5: for each 5-inp ut cut u of n do 6: t ← GetTru th ( u ) 7: ( t canon , T r ans ) ← Canoni caliz e ( t ) 8: for each candid ate c ircuit c in C t canon do 9: Connec tToLe aves ( N , c , u , T rans ) 10: N save d ← Derefe rence ( N , u ) 11: N added ← Refere nce ( N , c ) 12: N gain ← N save d − N added 13: Derefe rence ( N , c ) 14: Refere nce ( N , u ) 15: if N gain ≥ 0 and N b es t < N gain then 16: N best ← N gain 17: c best ← c 18: u best ← u 19: end if 20: end for 21: end f or 22: if N best = − 1 then 23: continue 24: end if 25: Derefe rence ( N , u best ) 26: Refere nce ( N , c best ) 27: end for In [1 8], th e author s pr oposed an op timization flow com- posed of ba lance , re write and r efa ctor pr ocesses, and imple- mented it in the tool ABC [6] with the script r esyn2 . Compare d to [18], rewriting using 5-inpu t cu ts explo its larger cuts and more rep lacement options, thus has the poten tial for getting r e syn2 script out of local m inima, pr oviding b etter rewriting oppor tunities. V . E X P E R I M E N T A L R E S U LT S The presented algorithm is implem ented using structu rally hashed AI G as an inter nal circuit r epresentation an d integrated in ABC synth esis tool as a comm and r ewrite5 . T o evaluate its effectiveness, we p erforme d a set of exper iments using IWLS 2005 bench marks [2 0] w ith more than 5000 AIG nodes after structu ral hash ing. All experimen ts were ca rried out on a lapto p w ith Intel Co re i7 1.6GHz ( 2.8GHz m aximum frequen cy) quad -core proce ssor , 6 MB cache, an d 4 GB RAM. First, for each b enchmar k, we applied a sequen ce of com- mands r esyn2; re write5; r esyn2 in the mod ified ABC an d compare d the resu lt to two co nsecutive runs of r esyn2 without r ewrite5 in betwee n. The results are summarized in T ab le I. Colu mns labeled by A give the area in terms o f AIG nodes. Column s labeled by t giv e the runtime . Th e impr ovement of are a an d the incr ease of runtime are then calculated and shown in the last two colum ns. T able I sho ws that the a verage improvemen t in area achie ved by add ing r ewrite5 in between two resyn2 runs is 3.50%, at the cost of 33.1 8% o f extra ru ntime. This result indica tes that the pr oposed re write5 me thod is effecti ve in brin ging ABC’ s r e syn2 optimizatio n script ou t of local minim a, lead ing to better optimization possibilities. The seco nd expe riment is perfo rmed similarly , except we used a long er o ptimization flow: r esyn2; re write5; resyn2; r ewrite5; res yn2 . The result is compar ed to three consecutive runs of r esyn 2 script. The result o f the second experiment is shown in T able II, which h as the same stru cture as T ab le I. The average improve- ment in area u sing the new optimizatio n flow is 4.88%, at the cost of 46.1 1% o f extra r untime. Th is result shows the possibility to fur ther extend the r e syn2 sequenc e b y inserting r ewrite5 run s, to achieve even better optimization . Even long er optim ization flows were also tested. T he compariso n of average resu lts is sum marized in T able III. The im provement in area conver ges after certain num ber of r e syn2 - r ewrite5 iterations. The increase of imp rovement is insignificant for more than four r uns of r esyn2 . improv ement in area e xtra runtime SS → SWS 3.50% 33.18% SSS → SWSW S 4.88% 46.11% SSSS → SWS WSWS 5.39% 47.48% SSSSS → SWSWSWSW S 5.57% 51.21% NO TE: S stands for resyn2 ; W stands for rewrit e5 . T ABLE III S U M M A RY O F A V E R AG E R E S U LT S . V I . C O N C L U S I O N In this paper, we pr esent an AI G-based rewriting techn ique that uses 5-inpu t cuts. The technique extend s th e a pproach of AIG rewriting u sing 4-inpu t cuts p resented in [18]. Expe ri- mental results show that ou r algorithm is effecti ve in driving other op timization techn iques, such as r esyn2 scrip t in ABC, out o f lo cal m inima. T he proposed r ewriting technique m ight be usef ul in a new optimiza tion flow comb ining rewriting of both 4-input and 5-input cuts. R E F E R E N C E S [1] R. K . Brayton, A. L. Sangio v anni-V incent elli, C. T . McMulle n, and G. D. Hachtel, Logic Minimizat ion Algorithms for V LSI Synthesis . Norwell, MA, USA: Kluwer Academic Publishers, 1984. [2] J. A. Darringer , D. Brand, J. V . Gerbi, W . H. Joyner , and L. Tre villya n, “LSS: A system for production logic synthesis, ” IBM Jou rnal of Re- sear ch and Devel opment , vol. 28, no. 5, pp. 537 –545, 1984. [3] D. Gregory , A. de Geus, K. Bartlett , and G. Hachtel, “SOCRA TES: A system for automati cally synthesizing and optimiz ing combination al logic, ” in Design Automat ion, 1986. 23rd Confere nce on , 1986, pp. 79 – 85. 5 resyn2;re syn2 resyn2;re write5;resyn2 benchmark no des A 1 t 1 , s ec A 2 t 2 , sec ( A 1 − A 2 ) / A 1 ( t 2 − t 1 ) / t 1 ac97 ctrl 14244 10222 0.759 10212 0.921 0.10% 21.34% aes core 21522 20153 3.125 19945 4.079 1.03% 30.53% b14 1 9471 5902 1.299 4712 1.929 20.16% 48.50% b15 1 17015 10215 2.067 10012 2.204 1.99% 6.63% b17 1 51419 31447 5.364 30943 6.948 1.60 % 29.53% b18 1 130418 81185 18.947 78430 25.344 3.39% 33.76% b19 1 254960 153796 37.618 149269 47.708 2.94% 26.82% b20 1 21074 13635 2.666 12048 3.819 11 .64% 43.25% b21 1 20538 12845 2.618 10940 3.900 14.83% 48.97% b22 1 31251 19698 4.109 16986 5.870 13.77% 42.86% des perf 82650 73724 15.717 73224 23.228 0.68% 47.79% DMA 24389 22306 2.524 20269 3.129 9 .13% 23.97% DSP 44759 37976 5.635 37728 7.734 0.65% 37.25% etherne t 86650 55925 5.790 55838 7.879 0.16% 36.08% leon2 788737 774919 142.645 774065 187.660 0. 11% 31.56% mem ctrl 15325 8518 1.255 8449 1.511 0.81 % 20.40% netca rd 803723 516124 93.952 516001 122.749 0.02% 30.65% pci bridge32 22790 16362 1.719 16271 2.288 0.56% 33.10% s35932 8 371 7843 0.755 7843 1.003 0.00% 32.85% s38417 9 062 7969 0.812 7936 1.149 0.41% 41.50% s38584 8 477 7224 0.720 7188 0.921 0.50% 27.92% systemcaes 12384 9614 1.705 9391 2.602 2.32% 52.61% tv80 9635 7084 1.169 6970 1.498 1.61% 28.14% usb funct 15826 13082 1.439 12892 1.858 1.45% 29.12% vga lcd 126696 88641 10.517 88659 14.268 -0.02% 35.67% wb conmax 47853 39163 4.748 38701 5.791 1.18% 21.97% A verag e 3.50% 33.18% T ABLE I E FFE C T I V E N E S S O F I M P ROV I N G D O U B L E resyn2 O P T I M I Z AT I O N FL O W US I N G re write 5 , O N I W L S 2 0 0 5 BE N C HM A R K S . resyn2;re syn2;resyn2 resyn2;re write5;resyn2; re write5; resyn2 benchmark nodes A 1 t 1 , s ec A 2 t 2 , s ec ( A 1 − A 2 ) / A 1 ( t 2 − t 1 ) / t 1 ac97 ctrl 14244 10202 1 .084 10180 1.396 0.22% 28.78% aes core 21522 20044 4.562 19554 6.646 2. 44% 45.68% b14 1 9471 5652 1.702 4350 2.526 23.04% 48.41% b15 1 17015 10029 2.335 9796 3.231 2.32% 38.37% b17 1 51419 30107 7.446 29248 10.530 2.85% 41.42% b18 1 130418 79204 24.658 74827 38.047 5. 53% 54.30% b19 1 254960 149177 49.815 143633 70.876 3.72% 42.28% b20 1 21074 13405 3.811 10732 5.878 19.94% 54.24% b21 1 20538 12240 3.603 9379 5.437 23.37% 50.90% b22 1 31251 18967 5.614 15186 8.595 19.93% 53.10% des perf 82650 73248 23.235 72322 36.941 1.26% 58.99% DMA 24389 22288 3.573 20214 4.874 9.31% 36.41% DSP 44759 37634 8.055 37273 12.465 0.96% 54.75% etherne t 86650 55803 8.287 55794 12.067 0.02% 45.61% leon2 788737 774560 213.921 773399 352.054 0. 15% 64.57% mem ctrl 15325 8408 1.726 8313 2.260 1.13% 30.94% netca rd 803723 515961 133.294 515771 181.877 0. 04% 36.45% pci bridge32 22790 16313 2. 385 16235 3.650 0.48% 53.04% s35932 8 371 7843 1.034 7843 1.457 0.00% 40.91% s38417 9 062 7947 1.158 7886 1.725 0.77% 48.96% s38584 8 477 7217 1.021 7199 1.312 0.25% 28.50% systemcaes 12384 9595 2.258 9248 4.043 3.62% 79.05% tv80 9635 7030 1.618 6879 2.308 2.15% 42.65% usb funct 15826 13041 2.037 12784 2.880 1.97% 41.38% vga lcd 126696 88621 15.258 88687 22.223 -0.07% 45.65% wb conmax 47853 38676 6. 759 38095 9.032 1.50% 33.63% A verag e 4.88% 46.11% T ABLE II E FFE C T I V E N E S S O F I M P ROV I N G T R I P L E re syn2 O P T I M I Z A T I O N F L O W U S I N G r ewrit e5 , O N I W L S 2 0 0 5 B E N C H M A R K S . 6 [4] J. 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