A Logic Programming Framework for Combinational Circuit Synthesis

A Logic Programming F ramew ork for Com binational Circuit Syn thesis P aul T arau Departmen t of Computer Science and Engineering Univ ersity of North T exas p aul.tar au@gmail.c om Brenda Luderman In tel Corp. Austin, T exas br enda.luderman@gmail.c om Abstract. Logic Programming languages and combination al circuit syn- thesis to ols share a common “combinatorial searc h ov er logic formulae” bac kground. This pap er attempts to reconnect the tw o fields with a fresh lo ok at Prolog enco dings for the com binatorial ob jects in volv ed in circuit syn thesis. While b enefiting from Prolog’s fast unification algorithm and built-in bac ktracking mechanism, efficiency of our searc h algorithm is en- sured by using parallel bitstring op erations together with logic v ariable equalit y propagation, as a mapping mec hanism from primary inputs to the leav es of candidate Leaf-DA Gs implementing a com binational cir- cuit sp ecification. After an exhaustive expressiv eness comparison of v ari- ous minimal libraries, a surprising first-runner, Strict Boolean Inequality “ < ” together with constant function “1” also turns out to hav e small transistor-coun t implementations, competitive to NAND-only or NOR- only libraries. As a practical outcome, a more realistic circuit syn thesizer is implemented that com bines rewriting-based simplification of ( <, 1) cir- cuits with exhaustiv e Leaf-D AG circuit searc h. Keyw ords : lo gic pr o gr amming and cir cuit design, c ombinatorial obje ct gener ation, exact c ombinational cir cuit synthesis, universal b o ole an lo gic libr aries, symb olic r ewriting, minimal tr ansistor-c ount cir cuit synthesis 1 In tro duction V arious logic programming applications and circuit synthesis tools share algo- rithmic techniques ranging from search ov er combinatorial ob jects and constraint solving to sym b olic rewriting and co de transformations. The significant semantic distance b etw een the tw o fields, coming partly from the application fo cus and partly from the hardw are/softw are design gap has b een also widened b y the use of low er lev el procedural languages for implement- ing circuit design to ols - arguably for pro viding b etter p erformance fine tuning opp ortunities. While in trigued b y the seman tic and terminological gap betw een the t w o fields, our in terest in the use of logic programming for circuit design has b een encouraged b ecause of the follo wing facts: – the simplicity and elegance of combinatorial generation algorithms in the con text of Prolog’s bac ktracking, unification and logic grammar mec hanisms – the structural similarit y b et ween Prolog terms and the Leaf-D AGs typically used as a data structure for syn thesized circuits – elegan t implemen tations of circuit design to ols in high lev el functional lan- guages [10] – the presence of new flexible constraint solving Prolog extensions like CHR [6] that could express lay out, routing and technology mapping aspects of the circuit design pro cess needed, b esides circuit syn thesis, for realistic design to ols. The pap er summarizes our efforts on solving some realistic com binational circuit synthesis problems with logic programming to ols. It is organized as fol- lo ws. Section 2 describes the generation of com binatorial ob jects needed for exact circuit syn thesis in Prolog, section 3 shows uniform bitstring represen tations for functions and primary inputs that c heck function equiv alence without backtrac k- ing. Section 4 compares v arious univ ersal b o olean function libraries in terms of total cost of minimal represen tations of the set of 16 2-argumen t op erators as an indicator of expressiveness for minimal cost synthesis purp oses. As result of this comparison, section 5 focuses on a surprisingly in teresting library consisting of Strict Boolean Inequalit y and constant function 1 with subsection 5.1 sho wing univ ersality of ( <, 1) and subsection 5.2 presenting our library sp ecific rewriting algorithm, usable as minimization heuristics when exact syn thesis b ecomes in- tractable. Section 6 describ es lo w transistor-count implemen tations of the < -gate and compares transistor counts for ( <, 1) with equiv alen t NAND-based circuits. Sections 7 and 8 discuss related and future w ork and section 9 concludes the pa- p er. The Prolog co de for the exact synthetizer and v arious libraries is av ailable at http://logic.csci.unt.edu/tarau/research/2007/csyn.zip . 2 Com binatorial Ob jects and Combinational Circuit Syn thesis Our exact synthesis algorithm uses Prolog’s depth-first backtrac king to find min- imal circuits represen ting b o olean functions, based on a giv en library of primi- tiv es, through composition of com binatorial generation steps and efficient c heck- ing against an output pattern sp ecified as a truth table. The general structure of the algorithm is as follows: Through the paper, Leaf-DA Gs will b e used to represen t the syn thetized circuits. The general structure of the algorithm is as follows: 1. First, the algorithm runs a library sp ecific rewriting mo dule (see 5.2 for a library specific rewriting mo dule) on the input formula (in symbolic, CNF or DNF form). This (or a conserv ativ e higher estimate) provides an upper limit (in terms of a cost function, for instance the num b er of gates) on the size of the syn thesized expression. It also provides a (heuristically) minimized form ula, in therms of the library , that can b e returned as output if exact syn thesis times out. 2. Next, if the formula qualifies for exact synthesis, w e enumerate candidate trees in incr e asing c ost or der , to ensure that minimal trees are generated first. This in volv es the following steps: (a) First, w e implemen t a mapping from the set primary inputs to the set of their occurrences in a tree. This inv olv es generating functions from N v ariables to M o ccurrences. W e achiev e this without term construction, through logical v ariable bindings, efficiently undone on backtrac king b y Prolog’s trailing mec hanism. (b) Next, N-no de binary trees of increasing sizes are generated. The combina- tion of the expression trees and the mapping of logic v ariables (represen t- ing primary inputs) to their (p ossibly multiple) occurrences, generates Leaf-D AGs. 3. Finally , we ev aluate candidate Leaf-DA Gs for equiv alence with the output sp ecification. W e will describe the details of the algorithm and the key steps of their Prolog implemen tation in the follo wing subsections. 2.1 Bo olean Expression T rees Size-constrained expression trees are com binatorial ob jects providing the skele- tons for the Leaf-D AGs generated b y our algorithm, as sho wn in predicate enumerate_tree_candidates/5 . The constraints are expressed as input pa- rameters UniqueVarAndConstCount and LeafCount . The generator pro duces an expression tree ETree and computes its truth table OutSpec enco ded as a bitstring-in teger. Size-constraints, ensuring termination of the recursiv e predi- cate generate_expression_tree/7 , are enco ded as a finite list of nodes, using DCG notation. T ermination is ensured b y ha ving each recursive step consume exactly one no de. A finite list of leaf v ariables pro vides leav es to the generated tree in the first clause of predicate generate_expression_tree/7 . enumerate_tree_candidates(UniqueVarAndConstCount,LeafCount, Leaves,ETree,OutputSpec):- N is LeafCount-1, length(Nodes,N), generate_expression_tree(UniqueVarAndConstCount,ETree,OutputSpec, Leaves,[],Nodes,[]). generate_expression_tree(_,V,V,[V|Leaves],Leaves)-->[]. generate_expression_tree(NbOfBits,ETree,OutputSpec,Vs1,VsN)-->[_], generate_expression_tree(NbOfBits,L,O1,Vs1,Vs2), generate_expression_tree(NbOfBits,R,O2,Vs2,VsN), {combine_expression_values(NbOfBits,L,R,O1,O2,ETree,OutputSpec)}. The predicate combine_expression_values/7 , sho wn b elow for the ( ∗ , ⊕ , 1) library , produces tree nodes lik e L*R and L^R , while computing their bitstring- in teger enco ded truth table O from the left and righ t branc h v alues O1 and O2 . combine_expression_values(_,L,R,O1,O2, L*R,O):-bitand(O1,O2,O). combine_expression_values(_,L,R,O1,O2, L^R,O):-bitxor(O1,O2,O). The generated trees ha v e binary operators as in ternal no des and v ariables as lea ves. They are counted b y Catalan n umbers [15]), with 4 N as a (rough) upper b ound for N leav e trees. 2.2 Implemen ting Finite F unctions as Logical V ariable Bindings W e express finite functions as bindings of a list of logic v ariables (the range of the function) to v alues in the domain of the function. functions_from([],_). functions_from([V|Vs],Us):-member(V,Us),functions_from(Vs,Us). Example: A call like ?- functions_from([A,B,C],[0,1]) enumerates the 8 functions as variable bindings like: {A->0,B->0,C->0} {A->0,B->0,C->1} ... {A->1,B->1,C->1} Assuming the first set has M elements and the second has N elements, a total of N M bac ktracking steps are inv olved in the enumeration, one for each function b et ween the tw o sets. As a result, a finite function can b e seen simply as a set of v ariable o ccurrences. This pro vides fast combinatorial enumeration of function ob jec ts, for whic h backtrac king only inv olv es trailing of v ariable addresses and no term construction. 2.3 Leaf-D AG Circuit Represen tations for Com binational Logic Definition 1 A Leaf-D AG is a dir e cte d acyclic gr aph wher e only vertic es (c al le d le aves) that have no outgoing e dges c an have multiple inc oming e dges. Leaf-D AGs can b e seen as trees with pos sibly merged leav es. Note that Leaf- D AGs are naturally represented as Prolog terms with multiple o ccurrences of some v ariables - like X and Y in f ( X , g ( X , Y , Z ) , Y ). Our Leaf-DA G generator com bines the size-constrained tree generator from subsection 2.1 and the functions-as-bindings generator from subsection 2.2, as follo ws: generate_leaf_dag(UniqueVarAndConstCount,LeafCount, UniqueVarsAndConsts,ETree,OutputSpec):- length(Leaves,LeafCount), functions_from(Leaves,UniqueVarsAndConsts), enumerate_tree_candidates(UniqueVarAndConstCount,LeafCount, Leaves,ETree,OutputSpec). Prop osition 1 L et catal an ( M ) denote the M-th Catalan numb er. The total b acktr acking steps for gener ating al l L e af DA Gs with N primary inputs and M binary op er ation no des is catal an ( M ) ∗ N M +1 . Pr o of. It follows from the fact that Catalan num b ers count the trees and N M +1 coun ts the functions corresp onding to mapping the primary inputs to their lea ves, b ecause a binary tree with M in ternal nodes, eac h corresponding to an op eration, has M + 1 leav es. Note that if constan t functions like 0 or 1 are part of the library , they are simply added to the list of primary inputs. The predicate synthesize_leaf_dag/4 describ es a (simplified version) of our Leaf-D AG generator. Note that if the OutputSp ec truth table is giv en as a constan t v alue, unification ensures that only LeafD AGs matching the sp ecifica- tion are generated. With OutputSp ec used as a free v ariable, the predicate can b e used in combination with Prolog’s dynamic database as part of a dynamic programming algorithm that tables and reuses sub circuits to av oid recomputa- tion. synthesize_leaf_dag(MaxGates,UniqueBitstringIntVars, UniqueVarAndConstCount,PIs:LeafDag=OutputSpec):- constant_functions(UniqueVarAndConstCount,ICs,OCs), once(append(ICs,UniqueBitstringIntVars,UniqueVarsAndConsts)), for(NbOfGates,1,MaxGates), generate_leaf_dag(UniqueVarAndConstCount,NbOfGates, UniqueVarsAndConsts,ETree,OutputSpec), decode_leaf_dag(ETree,UniqueVarsAndConsts,LeafDag,DecodedVs), once(append(OCs,PIs,DecodedVs)). Prop osition 2 The pr e dic ate synthesize_leaf_dag/4 gener ates L e af-D AGs in incr e asing size or der. Pr o of. It follows from the fact that each call to generate_leaf_dag/5 enumer- ates on backtrac king all Leaf-DA Gs of size NbOfGates and the predicate for/3 pro vides increasing NbOfGates b ounds. Assuming zero cost for constant functions and a fixed transistor cost for eac h op erator, it follows that the synthesizer pro duces circuits based on single- op er ator libraries in increasing cost order. F or more complex cost mo dels adap- tations to the tree generator can b e implemented easily . 3 F ast Bo olean Ev aluation with Bitstring T ruth T able Enco dings W e use an adaptation of the clev er bitstring-in teger enco ding described in the Bo olean Ev aluation section of [7] of n v ariables as truth tables. Let x k b e a v ariable for 0 ≤ k < n . Then x k = (2 2 n − 1) / (2 2 n − k − 1 + 1), where the num b er of distinct v ariables in a b o olean expression gives n , the num b er of bits for the enco ding. The mapping from v ariables, denoted as integers, to their truth table equiv alen ts, is provided b y the following Prolog co de: % Maps variable K in 0..Mask-1 to truth table % Xk packed as a bitstring-integer. var_to_bitstring_int(NbOfBits,K,Xk):- all_ones_mask(NbOfBits,Mask), NK is NbOfBits-(K+1), D is (1<<(1< B , and b oth express ( A ⊕ B ⊕ C ) as ( A = ( B = C )). Note also, that b esides sp otting out the minimal universal library ( <, 0), the comparison also identifies ( <, nor, 1) as a highly expressive library , with p otential for practical design uses, giv en that < and nor hav e both lo w transistor-coun t implemen tations. Finally , one of the ov erall “winners” of the comparison is ( <, = , 1). It ex- presses the 16 op erators with only 21 gates and it is a sup erset of the ( <, 1) library . This also suggests exploring in more detail the potential of < for syn- thesis. 5 Using Strict Bo olean Inequality for Com binational Circuit Syn thesis While Strict Bo olean Inequalit y 1 A < B together with 1 is a universal bo olean function pair, it has b een neglected b y logicians as well as circuit designers, to the p oint where there are surprisingly few references to it in the literature in b oth fields. Interestingly enough, its dual , ( ⇒ , 0) 2 – is a well kno wn universal function pair that has been extensively studied as an axiomatic basis for b oth classical and in tuitionistic prop ositional logic. One can only sp eculate ab out the reasons for this neglect. The lack of alge- braic grouping prop erties lik e comm utativity and asso ciativity comes to mind. Or, that its intuitiv e meaning would b e harder to map to common reasoning patterns. In an y case, none of these are critical for the syn thesis problem, which, stated generically , is about finding minimal r epr esentations of finite functions 3 in terms of a universal subset of them, giv en as a libr ary . As an indication of the usefulness of ( <, 1) for syn thesis, let’s note that A ⊕ B (kno wn to b e part of notoriously hard to synthesize b o olean functions) is in fact ( A < B ) + ( B < A ) and therefore A < B can provide half of A ⊕ B . Note that it also provides a form of conjunction (with first argumen t in verted), given its equiv alence to ∼ A ∗ B . It follo ws from this equiv alence, that < also works as an inference rule: from its truth, one can determine uniquely the truth v alues of b oth of its arguments, i.e. the first should be false and the second true . As a side note, the reader migh t notice that this is similar, but in a w ay stronger than the mechanism through which Mo dus Ponens works. In the case of Mo dus P onens, if one lo oks at its premises as a formula, then A ∗ ( A ⇒ B ) is equiv alent to A ∗ B implying the truth of B in addition to the (already assumed) truth of A . The key difference, that makes Mo dus P onens more intuitiv e is, of course, 1 (Equiv alent to ( ∼ A ) ∗ B as well as ∼ ( A ⇐ B )). Called Con verse Nonimplication as well as ”NOT A BUT B” by Kn uth [7]. Also called NIF standing for NOT (A IF B) and Half-XOR. 2 Logical Implication with F alseho od (also denoted ⊥ ) 3 All finite functions can be expressed as b o olean functions, by using binary enco dings of their arguments and v alues. that it provides an inference mechanism that conserves and extends truth, while using A < B as an inference mechanism w ould force one to deal with b oth true and false consequences. 5.1 Strict Boolean Inequality as a Univ ersal Bo olean Op erator Definition 3 Strict Bo ole an Ine quality is define d by the fol lowing truth table: A B A < B 0 0 0 0 1 1 1 0 0 1 1 0 Prop osition 3 Strict Bo ole an Ine quality A < B to gether with c onstant function 1 is a universal b o ole an function. Pr o of. Given that conjunction and negation form a universal b o olean function pair, the proposition follo ws from the fact that c onjunction A ∗ B has the same truth table as ( A < 1) < B and that negation ∼ A has the same truth table as ( A < 1). 5.2 The Sym b olic Rewriting Algorithm Our symbolic rewriting recurses o ver a giv en formula, and after each rewriting step, it pro ceeds with simplifications using prop ositional tautologies. W e will illustrate the algorithm with the table in Fig. 2 sho wing how v arious expressions are transformed after the recursive rewriting of their arguments. F or a giv en argumen t A we denote ‘ A the result of recursive application of the algorithm to A . The algorithm preserv es constants and primary input v ariables unchanged. W e also assume that simplification o ccurs implicitly after each transformation step. The algorithm reduces most simple tautologies to 1 and most simple contra- dictions to 0. As a result, it also may reduce the num b er of v ariables on whic h the expression actually dep ends. Optimizing for Minimal T r ansistor Count Giv en that constan t function 1 is 0- cost and that function < has a 4-transistor cost (see section 6), the synthesis algorithm can assume that the cost is given by the num b er of < gates. Delay-Constr aine d Minimal Cir cuit Synthesis Given the uniform gate structure of the circuits, we can ensure that delays are within acceptable margins b y simply constraining the maxim um length of the longest path from the primary inputs to the primary outputs. F rom T o 0 0 1 1 A < B ‘ A < ‘ B ∼ A ‘ A < 1 A ⇐ B (‘ A < ‘ B ) < 1 A ∗ B (‘ A < 1) < ‘ B nor ( A, B ) ‘ A < (‘ B < 1) A + B ‘( A ⇐ ( ∼ B )) A ⇒ B (‘ B < ‘ A ) < 1 A ⊕ B (‘ A < ‘ B ) + (‘ B < ‘ A ) A = B ‘( nor (( A < B ) , ( B < A )) < 1) ite ( C, T , F ) ‘(( C ⇒ T ) ∗ ( ∼ C ⇒ F )) Fig. 2. ( <, 1)-Rewriting Rules 5.3 Minimal ( <, 1)-representations for Key Bo olean F unctions Figure 3 shows minimal represen tations for 0, negation, some 2-input bo olean functions and the 3-argument IF-THEN-ELSE, as pro duced by our syn thesizer. In terestingly enough, the minimal form ulae obtained by exhaustiv e search are iden tical (as in the case of most simple formulae) with those obtained using our rewriting algorithm. F unction “ < ” Repr esentation 0 1 < 1 ∼ A A < 1 A ∗ B ( A < 1) < B A + B ( A < ( B < 1)) < 1 A ⇒ B ( B < A ) < 1 A ⇐ B ( A < B ) < 1 A ⊕ B (( A < B ) < (( B < A ) < 1)) < 1 A = B ( A < B ) < (( B < A ) < 1) A NAND B (( A < 1) < B ) < 1 A NOR B A < ( B < 1) IF A THEN B ELSE C ( A < ( C < 1)) < (( B < A ) < 1) Fig. 3. ( <, 1)-Representations of some functions 5.4 Syn thesis from CNF and DNF forms As Disjunctive Normal F orms (DNF, also called sum-of-pro ducts) and Conjunc- tiv e Normal F orms (CNF , also called product-of-sums) are the result of repeated conjunctions and disjunctions, we first fo cus on optimal ( <, 1)-representation of these. Prop osition 4 A se quenc e of disjunctions of N variables has a minimal ( <, 1) - r epr esentation with 2 o c curr enc es of c onstant 1 and exactly one o c curr enc e of e ach input variable, pr ovide d by the formula: A 1 + A 2 + . . . + A N = ( A 1 < ( A 2 < . . . ( A N < 1) . . . )) < 1 Prop osition 5 A se quenc e of c onjunctions of N variables has a minimal ( <, 1) - r epr esentation with N − 1 o c curr enc es of c onstant 1 and exactly one o c curr enc e of e ach input variable, pr ovide d by the formula: A 1 ∗ A 2 ∗ . . . A N − 1 ∗ A N = (( A 1 < 1) < (( A 2 < 1) < . . . (( A N − 1 < 1) < A N ) . . . ) Pr o of. By induction on the num b er of input v ariables, N. Syn thesis from CNF and DNF form ulae (that can b e obtained directly from truth table descriptions of circuits) pro ceeds by applying the enco dings provided b y the previous prop ositions recursively , follow ed by (and in terleav ed with) sim- plification steps. 6 T ransistor Implemen tations for ( <, 1)-circuits Clearly as A < B is equiv alent to nor ( A, ∼ B ), an ob vious 6-transistor im- plemen tation is obtained when input B drives a 2-transistor inv erter while its output and input A drive a 4-transistor NOR gate. This logic circuit is shown in Fig. 4. The output no de, A < B , has a direct path to the pow er no des VDD and VSS through the source connections of the transistors connected to it. As a result, the output is called “buffered” and the logic circuit type is “p o wered”. Fig. 4. P ow ered 6-T ransistor A < B T o reduce transistor coun t, a p ass tr ansistor lo gic (PTL) circuit for A < B can b e implemented using 4 transistors. In this circuit, the output no de, A < B , in Fig. 5 has a direct path to the p ow er net VSS while input B provides the VDD p o wer. Therefore, the logic circuit type is “semi-p ow ered” and the output lev el for VDD is called “un buffered”. Fig. 5. Semi-P ow ered 4-T rans. A < B The constant function 1 can b e implemented b y direct routing to the VDD p o wer grid. Similary , the constant function 0 can b e implemented b y direct routing to the VSS p o wer grid. In c onclusion, assuming a design using PTL-lo gic, the tr ansistor c ount for an implementation of the < function is 4, while c onstant functions 1 and 0 ar e essential ly fr e e, with tr ansistor c ount 0. T ransistor Coun t Comparisons for ( <, 1) and NAND. T o ha ve a glimpse at the competitiveness of ( <, 1) as a universal pair, in com- parison with a minimal NAND-based circuit, w e hav e compared costs obtained as transistor coun ts of the resulting circuits. While the comparison only inv olves Leaf-D AG representations and ignores the fact that stronger sharing could b e present in the case of multiple outputs or the case arbitrary D AGs are used, it shows, at a small scale, that practical uses of the ( <, 1) for exact synthesis are likely to b e comp etitiv e. Note also that in practice comm utativity of NAND brings more sharing opp ortunities if general DA Gs are used and that b oth A < 1 and nand ( A, A ) can b e replaced with 2-transistor in verters. F unction < -cost NAND-cost A = B 4*4=16 5*4=20 A ⊕ B 5*4=20 5*4=20 A ∗ B 2*4= 8 3*4=12 (8 if sharing) ( A ∗ B ) ⇒ C 4*4=16 4*4=16 A ∗ B ∗ C 4*4=16 6*4=24 A + B + C 4*4=16 7*4=28 if-then-else 5*4=20 4*4=16 ( A ⇒ B ) ∗ ( B ⇒ C )) 4*4=16 5*4=20 nand ( A, B ) 3*4=12 1*4=4 A < B 1*4 5*4=20 (16 if sharing) 2x2 half-adder 20+8=28 20+12=32 Fig. 6. T ransistor Costs 7 Related W ork Men tions of Prolog for circuit simulation go bac k as early as [3]. P eter Reintjes in [12] men tions CMOS circuit design and Prolog as tw o Ele gant T e chnolo gies with p oten tial for interaction. Knuth in [7], section 7.1.2 mentions A < B as forming one of the 5 (out of 16) b o olean function used as part of a b o ole an chain (sequence of connected 2-argument bo olean functions) needed for synthesis b y exhaustiv e enumeration. Interestingly , the other 4 are: >, ∗ , + , ⊕ . Note that > is the symmetric of < , and that with its exception, ∗ , + , ⊕ hav e b een hea vily used in v arious syn thesis algorithms. This supports our intuition that < and > ’s p oten tial for synthesis is worth further exploration. Knuth also computes minimal representations of all 5-argument functions using a clever reduction to equiv alence classes and prov es that the cost for representing almost ev ery b oole an function of N-arguments in terms of b o olean c hains exceeds 2 N / N . Rewriting/simplification has b een used in v arious forms in recent w ork on m ulti-level synthesis [8,9] using non-SOP enco dings ranging from And-In verter Gates (AIGs) and XOR-AND nets to graph-based representations in the tra- dition of [1]. Interestingly , new synthesis targets, ranging from AIGs to cyclic com binational circuits [13], turned out to b e comp etitive with more traditional minimization based synthesis tec hniques. Synthesis of reversible circuits with p ossible uses in low-pow er adiabatic computing and quantum computing [14] ha ve emerged. Despite its sup er-exp onential complexity , exact circuit synthesis efforts ha ve b een rep orted successful for increasingly large circuits [5,7]. While [12] describ es the basics of CMOS tec hnology , we refer the reader interested in full background information for our transistor mo dels to [11]. 8 F uture W ork While w e hav e provided un usually low cost transistor models for < gates, the v alidation of their use in v arious context requires more extensive SPICE simu- lations as w ell precise area, dela y and p ow er estimates. The relative simplicity of A < B suggests its use in nov el analog or non- silicon designs provided that one can measure that signal A is in a giv en sense w eaker than B. Its relative expressiveness c hallenges, to some extent, the widely b eliev ed statement [4,2] that symmetric functions are genuinly more interesting for circuit synthesis. F uture work is needed to substan tiate our belief that this is not necessarily the case, based on the intuition that asymmetric op erators cov er a larger com binatorial space than their asso ciative/comm utative siblings. The dual of the ( <, 1) library , ( ⇒ , 0) has the same expressiv e p ow er as ( < , 1). It would b e interesting to see if one can find similar low-transistor count implemen tations as the ones shown in this pap er for ( <, 1). Given that ( ⇒ , 0) has b een used as a foundation of v arious implic ative formalizations of classic and in tuitionistic logics, stronger rewriting mec hanisms migh t be a v ailable for it than the ones w e describ ed in subsection 5.2 for ( <, 1), resulting in b etter heuristics for handling circuits for whic h exact synthesis is in tractable. On the general syn thesis algorithm side, it would b e in teresting to add tabling of subcircuits (through the use of a system lik e XSB or b y writing a sp ecial purp ose circuit store) to a void recomputation. Adapting in telligent bac ktracking mec hanisms like those used in mo dern SA T-solvers should also b e considered to impro ve p erformance. Giv en our focus – to p oint out the usefulness of a relatively simple and un- explored primitive < as a universal b o olean function with small transistor count implemen tation – w e ha ve not inv ested an implemen tation effort comparable to high quality synthesis to ols lik e [16]. An interesting developmen t w ould b e adapting a to ol like ab c [16] to sp ecifically use < as a primitive. 9 Conclusion W e hav e described a general logic programming based exact circuit syn thesis algorithm and sho wn how Prolog language features lik e logic v ariables and back- trac king can be used to provide efficient, a concise and elegant implementations. The syn thesis algorithm has b een used to identify the univ ersal b o olean func- tion pair ( <, 1) as a primitive for circuit synthesis, after noticing the p ossibility of a 4-transistor PTL-implemen tation. W e hav e also shown that, surprisingly , despite b eing non-comm utative and non-asso ciative, Strict Bo olean Inequalit y “ < ” allows very low transistor-coun t implemen tations of t ypical small circuits. W e ha ve also provided a rewriting-based simplification algortithm in terms of ( <, 1) that handles symbolic b oolean expressions as well as CNF or DNF forms. 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