Computer Science / Hardware Architecture

All posts under category "Computer Science / Hardware Architecture"

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RISC and CISC

RISC and CISC

RISC์™€ CISC๋Š” ์ปดํ“จํ„ฐ ์•„ํ‚คํ…์ฒ˜ ์„ค๊ณ„์—์„œ ๋‘ ๊ฐ€์ง€ ๊ทน๋‹จ์ ์ธ ์ ‘๊ทผ ๋ฐฉ์‹์„ ๋Œ€ํ‘œํ•˜๋ฉฐ, ๊ฐ๊ฐ์ด ํŠน์ • ์‹œ์ ์—์„œ์˜ ๊ธฐ์ˆ ์  ์š”๊ตฌ์‚ฌํ•ญ๊ณผ ์ œํ•œ ์กฐ๊ฑด์— ๋”ฐ๋ผ ๋ฐœ์ „ํ•ด์™”์Šต๋‹ˆ๋‹ค. ์ด ๋…ผ๋ฌธ์€ RISC์™€ CISC์˜ ์žฅ๋‹จ์ ์„ ๋น„๊ตํ•˜๊ณ  ํ˜„๋Œ€ ์ปดํ“จํŒ… ํ™˜๊ฒฝ์—์„œ์˜ ์ ํ•ฉ์„ฑ์„ ๋ถ„์„ํ•ฉ๋‹ˆ๋‹ค. 1. ์„ค๊ณ„ ์ฒ ํ•™์˜ ๋ฐฐ๊ฒฝ CISC ์•„ํ‚คํ…์ฒ˜๋Š” ์ดˆ๊ธฐ ์ปดํ“จํ„ฐ ์‹œ์Šคํ…œ์—์„œ ์ฃผ ๋ฉ”๋ชจ๋ฆฌ๊ฐ€ ์ œํ•œ์ ์ด์—ˆ๋˜ ์ƒํ™ฉ์—์„œ ๋ฐœ์ „ํ–ˆ์Šต๋‹ˆ๋‹ค. ์ด๋•Œ, ๋ณต์žกํ•œ ๋ช…๋ น์–ด ์ง‘ํ•ฉ์€ ํ”„๋กœ๊ทธ๋žจ ์ฝ”๋“œ๋ฅผ ๋” ์งง๊ฒŒ ๋งŒ๋“ค๊ณ  ๋ฉ”๋ชจ๋ฆฌ๋ฅผ ํšจ์œจ์ ์œผ๋กœ ์‚ฌ์šฉํ•  ์ˆ˜ ์žˆ๊ฒŒ ํ–ˆ์Šต๋‹ˆ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ์ด๋Ÿฌํ•œ ์„ค๊ณ„๋Š” ๋ช…๋ น์–ด ๊ธธ์ด ๋ณ€๋™๊ณผ ๋ณต์žกํ•œ ๋””์ฝ”๋”ฉ ๋ฌธ

Computer Science Hardware Architecture
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

This paper introduces Shenjing, a novel architecture that aims to achieve energy efficient deep neural networks (DNNs). The primary focus is on addressing the high energy consumption of DNNs, especially in on device AI applications where both computation and communication consume significant amounts

Emerging Technologies Neural Computing Network Computer Science Hardware Architecture

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